74LVC109 Dual JK Flip-flop Datasheet

74LVC109 Dual JK flip-flop with set and reset positive-edge trigger

FEATURES
• 5 V tolerant inputs for interfacing with 5 V logic
• Wide supply voltage range from 1.2 to 3.6 V
• CMOS low power consumption
• Direct interface with TTL levels
• Inputs accept voltages up to 5.5 V
• Complies with JEDEC standard no. 8-1A
• ESD protection HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V.
• Specified from −40 to +85 °C and −40 to +125 °C.

• The 74LVC109A is a high-performance, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.
• The 74LVC109A is a dual positive edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs.
• The set and reset are asynchronous active LOW inputs and operate independently of the clock input.
• The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JK design allows operation as a D-type flip-flop by tying the J and K inputs together.
• Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

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