74AC11074 FLIP-FLOP WITH CLEAR AND PRESET Datasheet

74AC11074
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

• Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
• EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process
• 500-mA Typical Latch-Up Immunity at 125°C
• Package Options Include Plastic Small-Outline (74AC11074D) and Thin Shrink Small-Outline (74AC11074PW) Packages, and Standard Plastic 300-mil DIPs (74AC11074N)

This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input that meets the setup-time requirements are transferred to the outputs on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.

The 74AC11074 is characterized for operation from -40°C to 85°C.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived 74AC11074 FLIP-FLOP WITH CLEAR AND PRESET Datasheet file may be downloaded here without warranties.