V320MTC

V320MTC Datasheet

V320 8-Bit Registered Bus Transceiver

Part	Datasheet
V320MTC	V320MTC (pdf)

Related Parts	Information
V320MTCX	V320MTCX

PDF Datasheet Preview
V320 8-Bit Registered Bus Transceiver V320 8-Bit Registered Bus Transceiver The V320 is an 8-bit universal bus transceiver designed for high speed interfacing with the VME320 backplane. It has output characteristics optimized for driving large capacitive loads and features modified input levels VIH/VIL for increased noise immunity and reduced input skew. The V320 functionality consists of bus transceiver circuits with 3-STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic level. OE and direction pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or B register or in both. The select controls can multiplex stored and real time transparent mode data. The direction control determines which bus will receive data when the enable control OE is active LOW. In the isolation mode OE HIGH A data may be stored in the B register and/or B data may be stored in the A register. s Independent registers for A and B buses s Multiplexed real-time and stored data s Guaranteed output skew s Guaranteed MOS Multiple Output Switching Specifica- tions s Output switching specified for both 50 pF and 250 pF, and 500 pF loads s Guaranteed simultaneous switching noise level VOLP/ VOLV and dynamic threshold performance VIHD/VILD s Glitch free power up/down high impedance for live inser- tion s BiCMOS technology for high drive and low power dissi- pation s −40°C to 85°C commercial temperature and VCC specifi- cations s Modified specifications across VCC and temperature VCC = 5.0V ±1%, T = 25°C ± 20°C present more realistic system conditions s Available in TSSOP MTC Ordering Code: Order Number Package Number Package Description V320MTC MTC24 24-Lead Thin Shrink Small Outline Package, JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names Direction A-to-B High B-to A Low Output Enable Active LOW CLKAB/SELAB A-to-B Clock/Select CLKBA/SELBA B-to-A Clock/Select A Inputs/Outputs TTL B Inputs/Outputs TTL 1998 Fairchild Semiconductor Corporation DS500149.prf V320 Functional Table D SELAB SELBA CLKAB CLKBA Function H or L H or L Isolation Input CLK A Data into A CLK B Data into A Reg. A to B Transparent CLK A Data into A Reg. H or L Input Output A Reg. to B Storage CLK A Data into A Reg. and B output B to A Transparent CLK B Data into B Reg. H or L Output Input B Reg. to A Storage L = Low H = High LH = Low to High transition X = Don’t Care CLK B Data into B Reg.and A output Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. V320 Absolute Maximum Ratings Note 1 DC Input Voltage VI DC Output Voltage VO Outputs 3-STATE Outputs Active Note 2 DC Output Sink Current into A-port/B-port IOL DC Output Source Current from A-port/B-port IOH DC Input Diode Current IIK VI < 0V ESD Rating typical Storage temperature TSTG Max IOL Current Applied to a

PDF Datasheet Preview

V320 8-Bit Registered Bus Transceiver

V320 8-Bit Registered Bus Transceiver

The V320 is an 8-bit universal bus transceiver designed for high speed interfacing with the VME320 backplane. It has output characteristics optimized for driving large capacitive loads and features modified input levels VIH/VIL for increased noise immunity and reduced input skew. The V320 functionality consists of bus transceiver circuits with 3-STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic level. OE and direction pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or B register or in both. The select controls can multiplex stored and real time transparent mode data. The direction control determines which bus will receive data when the enable control OE is active LOW. In the isolation mode OE HIGH A data may be stored in the B register and/or B data may be stored in the A register.
s Independent registers for A and B buses s Multiplexed real-time and stored data s Guaranteed output skew s Guaranteed MOS Multiple Output Switching Specifica-
tions s Output switching specified for both 50 pF and 250 pF,
and 500 pF loads s Guaranteed simultaneous switching noise level VOLP/

VOLV and dynamic threshold performance VIHD/VILD s Glitch free power up/down high impedance for live inser-
tion s BiCMOS technology for high drive and low power dissi-
pation s −40°C to 85°C commercial temperature and VCC specifi-
cations s Modified specifications across VCC and temperature

VCC = 5.0V ±1%, T = 25°C ± 20°C present more realistic system conditions s Available in TSSOP MTC
Ordering Code:

Order Number Package Number

Package Description

V320MTC

MTC24
24-Lead Thin Shrink Small Outline Package, JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names

Direction A-to-B High B-to A Low

Output Enable Active LOW

CLKAB/SELAB A-to-B Clock/Select

CLKBA/SELBA B-to-A Clock/Select

A Inputs/Outputs TTL

B Inputs/Outputs TTL
1998 Fairchild Semiconductor Corporation DS500149.prf

V320

Functional Table

D SELAB SELBA CLKAB CLKBA

Function

H or L H or L

Isolation

Input CLK A Data into A

CLK B Data into A Reg.

A to B Transparent

CLK A Data into A Reg.

H or L

Input Output A Reg. to B Storage

CLK A Data into A Reg. and B output

B to A Transparent

CLK B Data into B Reg.

H or L Output Input B Reg. to A Storage

L = Low H = High LH = Low to High transition X = Don’t Care

CLK B Data into B Reg.and A output

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

V320

Absolute Maximum Ratings Note 1

DC Input Voltage VI DC Output Voltage VO

Outputs 3-STATE

Outputs Active Note 2

DC Output Sink Current into A-port/B-port IOL

DC Output Source Current from A-port/B-port IOH

DC Input Diode Current IIK VI < 0V

ESD Rating typical

Storage temperature TSTG Max IOL Current Applied to a

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived V320MTC Datasheet file may be downloaded here without warranties.

Datasheet ID: V320MTC 634819