USB1T11ABQX

USB1T11ABQX Datasheet

USB1T11A Universal Serial Bus Transceiver

Part	Datasheet
USB1T11ABQX	USB1T11ABQX (pdf)

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USB1T11A Universal Serial Bus Transceiver USB1T11A Universal Serial Bus Transceiver The USB1T11A is a one chip generic USB transceiver. It is designed to allow 5.0V or 3.3V programmable and standard logic to interface with the physical layer of the Universal Serial Bus. It is capable of transmitting and receiving serial data at both full speed 12Mbit/s and low speed 1.5Mbit/s data rates. The input and output signals of the USB1T11A conform with the “Serial Interface Engine”. Implementation of the Serial Interface Engine along with the USB1T11A allows the designer to make USB compatible devices with off-theshelf logic and easily modify and update the application. s Complies with Universal Serial Bus specification s Utilizes digital inputs and outputs to transmit and receive USB cable data s Supports 12Mbit/s “Full Speed” and 1.5Mbit/s “Low Speed” serial data transmission s Compatible with the VHDL “Serial Interface Engine” from USB Implementers' Forum s Supports single-ended data interface s Single 3.3V supply s ESD Performance Human Body Model > kV on D−, D+ pins only > 4 kV on all other pins s 16-lead Pb-Free MLP package saves space Ordering Code: Order Number Package Number Package Description USB1T11AM Note 1 M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow USB1T11AM_NL M14A Pb-Free 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow USB1T11ABQX MLP16C Pb-Free 16-Terminal Molded Leadless Package MLP , JEDEC MO-220, 3mm square USB1T11AMTC Note 1 MTC14 14-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide USB1T11AMTC_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide USB1T11AMTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide Pb-Free package per JEDEC J-STD-020B. Note 1 Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagrams Pin Assignments for SOIC and TSSOP Pin Assignments for MLP 2005 Fairchild Semiconductor Corporation DS500234 USB1T11A Logic Diagram Pin Descriptions Pin Name RCV OE MODE VPO, VMO/FSEO VP, VM D+, D− SUSPND SPEED VCC GND I/O I AI/O I Description Receive data. CMOS level output for USB differential input Output Enable. Active LOW, enables the transceiver to transmit data on the bus. When not active the transceiver is in receive mode. Mode. When left unconnected, a weak pull-up transistor pulls it to VCC and in this GND, the VMO/FSEO pin takes the function of FSEO Force SEO . Inputs to differential driver. Outputs from SIE . MODE VMO/FSEO RESULT Logic “0” Logic “1” Logic “0” Logic “1” Illegal code Gated version of D− and D+. Outputs are logic “0” and logic Used to detect single ended zero SE0 , error conditions, and interconnect speed. Input to SIE . RESULT Low Speed Full Speed Error Data+, Data−. Differential data bus conforming to the Universal Serial Bus standard. Suspend. Enables a low power state while the USB bus is inactive. While the suspend pin is active it will drive the RCV pin to a logic “0” state. Both D+ and D− are 3-STATE. Edge rate control. Logic “1” operates at edge rates for “full speed”. Logic “0” operates edge rates for “low speed”. 3.0V to 3.6V power supply Ground reference USB1T11A Functional Truth Table Input Mode 0

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USB1T11A Universal Serial Bus Transceiver

USB1T11A Universal Serial Bus Transceiver

The USB1T11A is a one chip generic USB transceiver. It is designed to allow 5.0V or 3.3V programmable and standard logic to interface with the physical layer of the Universal Serial Bus. It is capable of transmitting and receiving serial data at both full speed 12Mbit/s and low speed 1.5Mbit/s data rates.

The input and output signals of the USB1T11A conform with the “Serial Interface Engine”. Implementation of the Serial Interface Engine along with the USB1T11A allows the designer to make USB compatible devices with off-theshelf logic and easily modify and update the application.
s Complies with Universal Serial Bus specification s Utilizes digital inputs and outputs to transmit and receive

USB cable data s Supports 12Mbit/s “Full Speed” and 1.5Mbit/s
“Low Speed” serial data transmission s Compatible with the VHDL “Serial Interface Engine”
from USB Implementers' Forum s Supports single-ended data interface s Single 3.3V supply s ESD Performance Human Body Model
> kV on D−, D+ pins only > 4 kV on all other pins s 16-lead Pb-Free MLP package saves space
Ordering Code:

Order Number

Package Number

Package Description

USB1T11AM Note 1

M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow

USB1T11AM_NL

M14A Pb-Free 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow

USB1T11ABQX

MLP16C Pb-Free 16-Terminal Molded Leadless Package MLP , JEDEC MO-220, 3mm square

USB1T11AMTC Note 1

MTC14 14-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide

USB1T11AMTC_NL

MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide

USB1T11AMTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
Pb-Free package per JEDEC J-STD-020B. Note 1 Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagrams

Pin Assignments for SOIC and TSSOP

Pin Assignments for MLP
2005 Fairchild Semiconductor Corporation DS500234

USB1T11A

Logic Diagram

Pin Descriptions

Pin Name RCV OE MODE

VPO, VMO/FSEO

VP, VM

D+, D− SUSPND SPEED

VCC GND

I/O I

AI/O I

Description Receive data. CMOS level output for USB differential input

Output Enable. Active LOW, enables the transceiver to transmit data on the bus. When not active the transceiver is in receive mode.

Mode. When left unconnected, a weak pull-up transistor pulls it to VCC and in this GND, the VMO/FSEO pin takes the function of FSEO Force SEO .

Inputs to differential driver. Outputs from SIE .

MODE

VMO/FSEO

RESULT

Logic “0”

Logic “1”

Logic “0”

Logic “1”

Illegal code

Gated version of D− and D+. Outputs are logic “0” and logic Used to detect single ended zero SE0 , error conditions, and interconnect speed. Input to SIE .

RESULT

Low Speed

Full Speed

Error

Data+, Data−. Differential data bus conforming to the Universal Serial Bus standard.

Suspend. Enables a low power state while the USB bus is inactive. While the suspend pin is active it will drive the RCV pin to a logic “0” state. Both D+ and D− are 3-STATE.

Edge rate control. Logic “1” operates at edge rates for “full speed”. Logic “0” operates edge rates for “low speed”.
3.0V to 3.6V power supply

Ground reference

USB1T11A

Functional Truth Table

Input

Mode 0

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Datasheet ID: USB1T11ABQX 634817