SSTV16859MTD

SSTV16859MTD Datasheet

SSTV16859 Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset

Part	Datasheet
SSTV16859MTD	SSTV16859MTD (pdf)

Related Parts	Information
SSTV16859G	SSTV16859G
SSTV16859GX	SSTV16859GX
SSTV16859MTDX	SSTV16859MTDX

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SSTV16859 Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset SSTV16859 Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset The SSTV16859 is a dual output 13-bit register designed for use with 184 and 232 pin DDR-1 memory modules. The device has a differential input clock, SSTL-2 compatible data inputs and a LVCMOS compatible RESET input. The device has been designed to meet the JEDEC DDR module register specifications. The device has been fabricated on an advanced submicron CMOS process and is designed to operate at power supplies of less than 3.6V’s. s Compliant with DDR-I registered module specifications s Operates at 2.5V ± 0.2V VDD s SSTL-2 compatible input structure s SSTL-2 compliant output structure s Differential SSTL-2 compatible clock inputs s Low power mode when device is reset s Industry standard 64 pin TSSOP package s Also packaged in plastic Fine-Pitch Ball Grid Array FBGA Ordering Code: Order Number Package Number Package Description SSTV16859G Note 1 Note 2 BGA96A 96-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide SSTV16859MTD Note 2 MTD64 64-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Note 1 Ordering code “G” indicates Trays. Note 2 Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. 2005 Fairchild Semiconductor Corporation DS500414 SSTV16859 Connection Diagrams Pin Assignment for TSSOP Pin Assignment for FBGA Top Thru View Pin Descriptions Pin Name Q1A-Q13A Q1B-Q13B D1-D13 SSTL-2 Compatible Register Outputs SSTL-2 Compatible Register Inputs RESET Asynchronous LVCMOS Reset Input Positive Master Clock Input VREF VDDQ VDD NC Negative Master Clock Input Voltage Reference Pin for SSTL level inputs Power Supply Voltage for Output Signals Power Supply Voltage for Inputs Electrically Isolated No Connect FBGA Pin Assignments B Q12A Q13A GND NC C Q10A Q11A GND NC Q8A Q9A VDDQ D13 Q6A Q7A VDDQ VDD D11 Q4A Q5A VDDQ VDD Q2A Q3A GND D7 RESET Q1A Q13B GND NC Q12B Q11B GND VREF NC K Q10B Q9B VDDQ VDD NC Q8B Q7B VDDQ VDD Q6B Q5B VDDQ D3 Q4B Q3B GND D1 Q2B Q1B GND NC Truth Table RESET Floating L = Logic LOW H = Logic HIGH X = Don’t Care but not floating unless noted = LOW-to-HIGH Clock Transition = HIGH-to-LOW Clock Transition Qn-1 = Output Remains in Previously Clocked State L H Qn-1 Qn-1 SSTV16859 Functional Description The SSTV16859 is a 13-bit dual register with SSTL-2 compatible inputs and outputs. Input data is transferred to output data on the rising edge of the differential clock pair. When the RESET signal is asserted LOW all outputs are placed into the LOW logic state and all input comparators are disabled for power savings. Output glitches are prevented by disabling the internal registers more quickly than the input comparators. When RESET is removed, the system designer must insure the clock and data inputs to the Logic Diagram device are stable during the rising transition of the RESET signal. The SSTL-2 data inputs transition based on the value of VREF. VREF is a stable system reference used for setting the trip point of the input buffers of the SSTV16859 and other SSTL-2 compatible devices. The RESET signal is a standard CMOS compatible input and is not referenced to the VREF signal. For n = 1 to 13

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SSTV16859 Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset

SSTV16859 Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset

The SSTV16859 is a dual output 13-bit register designed for use with 184 and 232 pin DDR-1 memory modules. The device has a differential input clock, SSTL-2 compatible data inputs and a LVCMOS compatible RESET input. The device has been designed to meet the JEDEC DDR module register specifications.

The device has been fabricated on an advanced submicron CMOS process and is designed to operate at power supplies of less than 3.6V’s.
s Compliant with DDR-I registered module specifications s Operates at 2.5V ± 0.2V VDD s SSTL-2 compatible input structure s SSTL-2 compliant output structure s Differential SSTL-2 compatible clock inputs s Low power mode when device is reset s Industry standard 64 pin TSSOP package s Also packaged in plastic Fine-Pitch Ball Grid Array

FBGA
Ordering Code:

Order Number Package Number

Package Description

SSTV16859G Note 1 Note 2

BGA96A
96-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide

SSTV16859MTD Note 2

MTD64
64-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Note 1 Ordering code “G” indicates Trays.
Note 2 Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
2005 Fairchild Semiconductor Corporation DS500414

SSTV16859

Connection Diagrams

Pin Assignment for TSSOP

Pin Assignment for FBGA Top Thru View

Pin Descriptions

Pin Name

Q1A-Q13A Q1B-Q13B D1-D13

SSTL-2 Compatible Register Outputs SSTL-2 Compatible Register Inputs

RESET Asynchronous LVCMOS Reset Input

Positive Master Clock Input

VREF VDDQ VDD NC

Negative Master Clock Input Voltage Reference Pin for SSTL level inputs Power Supply Voltage for Output Signals Power Supply Voltage for Inputs Electrically Isolated No Connect

FBGA Pin Assignments

B Q12A Q13A GND NC

C Q10A Q11A GND NC

Q8A Q9A VDDQ D13

Q6A Q7A VDDQ VDD D11

Q4A Q5A VDDQ VDD

Q2A Q3A GND D7 RESET

Q1A Q13B GND NC

Q12B Q11B GND VREF NC

K Q10B Q9B VDDQ VDD NC

Q8B Q7B VDDQ VDD

Q6B Q5B VDDQ D3

Q4B Q3B GND D1

Q2B Q1B GND NC

Truth Table

RESET

Floating

L = Logic LOW H = Logic HIGH X = Don’t Care but not floating unless noted = LOW-to-HIGH Clock Transition = HIGH-to-LOW Clock Transition Qn-1 = Output Remains in Previously Clocked State

L H Qn-1 Qn-1

SSTV16859

Functional Description

The SSTV16859 is a 13-bit dual register with SSTL-2 compatible inputs and outputs. Input data is transferred to output data on the rising edge of the differential clock pair. When the RESET signal is asserted LOW all outputs are placed into the LOW logic state and all input comparators are disabled for power savings. Output glitches are prevented by disabling the internal registers more quickly than the input comparators. When RESET is removed, the system designer must insure the clock and data inputs to the

Logic Diagram
device are stable during the rising transition of the RESET signal.

The SSTL-2 data inputs transition based on the value of VREF. VREF is a stable system reference used for setting the trip point of the input buffers of the SSTV16859 and other SSTL-2 compatible devices.

The RESET signal is a standard CMOS compatible input and is not referenced to the VREF signal.

For n = 1 to 13

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Datasheet ID: SSTV16859MTD 634789