SCAN182541ASSC
SCAN182541ASSC Datasheet
SCAN18541T Non-Inverting Line Driver with 3-STATE Outputs
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SCAN182541ASSC |
SCAN182541ASSC (pdf) |
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SCAN182541ASSCX |
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| SCAN18541T Non-Inverting Line Driver with 3-STATE Outputs SCAN18541T Non-Inverting Line Driver with 3-STATE Outputs The SCAN18541T is a high speed, low-power line driver featuring separate data inputs organized into dual 9-bit bytes with byte-oriented paired output enable control signals. This device is compliant with IEEE Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of Test Data Input TDI , Test Data Out TDO , Test Mode Select TMS , and Test Clock TCK . s IEEE JTAG Compliant s Dual output enable signals per byte s 3-STATE outputs for bus-oriented applications s 9-bit data busses for parity applications s Reduced-swing outputs source 32 mA/sink 64 mA s Guaranteed to drive transmission line to TTL input levels of 0.8V and 2.0V s TTL compatible inputs s 25 mil pitch SSOP Shrink Small Outline Package s Includes CLAMP and HIGHZ instructions s Member of Fairchild’s SCAN Products Ordering Code: Order Number Package Number Package Description SCAN18541TSSC MS56A 56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Names Pin Names AOE1, AOE2 BOE1, BOE2 Input Pins, A Side Input Pins, B Side 3-STATE Output Enable Input Pins, 3-STATE Output Enable Input Pins, Output Pins, A Side Output Pins, B Side A Side B Side Truth Tables AOE1 L H X L Inputs AOE2 L X H L Inputs BOE1 BOE2 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance 2000 Fairchild Semiconductor Corporation DS010965 SCAN18541T Block Diagrams Byte A Tap Controller Byte B Note BSR stands for Boundary Scan Register. SCAN18541T Description of Boundary-Scan Circuitry The scan cells used in the BOUNDARY-SCAN register are one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system data, while TYPE2 has the additional ability to control system data. Scan cell TYPE1 is located on each system input pin while scan cell TYPE2 is located at each system output pin as well as at each of the two internal active-high output enable signals. AOE controls the activity of the A-outputs while BOE controls the activity of the B-outputs. Each will activate their respective outputs by loading a logic high. The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low. cant bits of this captured value 01 are required by IEEE Std The upper six bits are unique to the SCAN18541T device. SCAN CMOS Test Access Logic devices do not include the IEEE optional identification register. Therefore, this unique captured value can be used as a “pseudo ID” code to confirm that the correct device is placed in the appropriate location in the boundary scan chain. Instruction Register Scan Chain Definition Bypass Register Scan Chain Definition Logic 0 The INSTRUCTION register is an 8-bit register which captures the default value of The two least signifi- Instruction Code All Others Instruction EXTEST SAMPLE/PRELOAD CLAMP HIGH-Z BYPASS Scan Cell TYPE1 Scan Cell TYPE2 SCAN18541T Description of Boundary-Scan Circuitry Continued Boundary-Scan Register Scan Chain Definition 42 Bits in Length SCAN18541T |
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