SCAN18245TSSC

SCAN18245TSSC Datasheet

SCAN18245T Non-Inverting Transceiver with 3-STATE Outputs

Part	Datasheet
SCAN18245TSSC	SCAN18245TSSC (pdf)

Related Parts	Information
SCAN18245TSSCX	SCAN18245TSSCX

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SCAN18245T Non-Inverting Transceiver with 3-STATE Outputs SCAN18245T Non-Inverting Transceiver with 3-STATE Outputs The SCAN18245T is a high speed, low-power bidirectional line driver featuring separate data inputs organized into dual 9-bit bytes with byte-oriented output enable and direction control signals. This device is compliant with IEEE Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundaryscan test logic and test access port consisting of Test Data Input TDI , Test Data Out TDO , Test Mode Select TMS , and Test Clock TCK . s IEEE JTAG Compliant s Dual output enable control signals s 3-STATE outputs for bus-oriented applications s 9-bit data busses for parity applications s Reduced-swing outputs source 32 mA/sink 64 mA s Guaranteed to drive transmission line to TTL input levels of 0.8V and 2.0V s TTL compatible inputs s 25 mil pitch SSOP Shrink Small Outline Package s Includes CLAMP and HIGHZ instructions s Member of Fairchild’s SCAN Products Ordering Code: Order Number Package Number Package Description SCAN18245TSSC MS56A 56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names G1, G2 Side A1 Inputs or 3-STATE Outputs Side B1 Inputs or 3-STATE Outputs Side A2 Inputs or 3-STATE Outputs Side B2 Inputs or 3-STATE Outputs Output Enable Pins DIR1, DIR2 Direction of Data Flow Pins 2000 Fairchild Semiconductor Corporation DS010961 SCAN18245T Truth Table Inputs G1 DIR1 H= HIGH Voltage Level L= LOW Voltage Level Functional Description The SCAN18245 consists of two sets of nine non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus-oriented applications. Direction pins DIR1 and DIR2 LOW enables data from B Ports to A Ports, when Block Diagrams Inputs G2 DIR2 X= Immaterial Z= High Impedance HIGH enables data from A Ports to B Ports. The Output Enable pins G1 and G2 when HIGH disables both A and B Ports by placing them in a high impedance condition. A1, B1, G1 and DIR1 A2, B2, G2 and DIR2 Note BSR stands for Boundary Scan Register. Note BSR stands for Boundary Scan Register. Tap Controller SCAN18245T Description of Boundary-Scan Circuitry The scan cells used in the BOUNDARY-SCAN register are one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system data, while TYPE2 has the additional ability to control system data. See IEEE Standard Figure for a further description of scan cell TYPE1 and Figure for a further description of scan cell TYPE2. Scan cell TYPE1 is located on each system input pin while scan cell TYPE2 is located at each system output pin as well as at each of the two internal active-high output enable signals. AOE controls the activity of the A-outputs while BOE controls the activity of the B-outputs. Each will activate their respective outputs by loading a logic high. The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low. Bypass Register Scan Chain Definition Logic 0 The two least significant bits of this captured value 01 are required by IEEE Std The upper six bits are unique to the SCAN18245T device. SCAN CMOS Test Access Logic devices do not include the IEEE optional identification register. Therefore, this unique captured value can be used as a “pseudo ID” code to confirm that the correct device is placed in the appropriate location in the boundary scan chain. Instruction Register Scan Chain Definition MSB LSB Instruction Code Instruction EXTEST SAMPLE/PRELOAD CLAMP HIGHZ The INSTRUCTION register is an eight-bit register which captures the value All Others BYPASS

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SCAN18245T Non-Inverting Transceiver with 3-STATE Outputs

SCAN18245T Non-Inverting Transceiver with 3-STATE Outputs

The SCAN18245T is a high speed, low-power bidirectional line driver featuring separate data inputs organized into dual 9-bit bytes with byte-oriented output enable and direction control signals. This device is compliant with IEEE Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundaryscan test logic and test access port consisting of Test Data Input TDI , Test Data Out TDO , Test Mode Select TMS , and Test Clock TCK .
s IEEE JTAG Compliant s Dual output enable control signals s 3-STATE outputs for bus-oriented applications s 9-bit data busses for parity applications s Reduced-swing outputs source 32 mA/sink 64 mA s Guaranteed to drive transmission line to TTL input
levels of 0.8V and 2.0V s TTL compatible inputs s 25 mil pitch SSOP Shrink Small Outline Package s Includes CLAMP and HIGHZ instructions s Member of Fairchild’s SCAN Products
Ordering Code:

Order Number Package Number

Package Description

SCAN18245TSSC

MS56A
56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names

G1, G2

Side A1 Inputs or 3-STATE Outputs Side B1 Inputs or 3-STATE Outputs Side A2 Inputs or 3-STATE Outputs Side B2 Inputs or 3-STATE Outputs Output Enable Pins

DIR1, DIR2 Direction of Data Flow Pins
2000 Fairchild Semiconductor Corporation DS010961

SCAN18245T

Truth Table

Inputs

G1 DIR1

H= HIGH Voltage Level L= LOW Voltage Level

Functional Description

The SCAN18245 consists of two sets of nine non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus-oriented applications. Direction pins DIR1 and DIR2 LOW enables data from B Ports to A Ports, when

Block Diagrams

Inputs

G2 DIR2

X= Immaterial Z= High Impedance

HIGH enables data from A Ports to B Ports. The Output Enable pins G1 and G2 when HIGH disables both A and B Ports by placing them in a high impedance condition.

A1, B1, G1 and DIR1

A2, B2, G2 and DIR2

Note BSR stands for Boundary Scan Register.

Note BSR stands for Boundary Scan Register.

Tap Controller

SCAN18245T

Description of Boundary-Scan Circuitry

The scan cells used in the BOUNDARY-SCAN register are one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system data, while TYPE2 has the additional ability to control system data. See IEEE Standard Figure for a further description of scan cell TYPE1 and Figure for a further description of scan cell TYPE2.

Scan cell TYPE1 is located on each system input pin while scan cell TYPE2 is located at each system output pin as well as at each of the two internal active-high output enable signals. AOE controls the activity of the A-outputs while BOE controls the activity of the B-outputs. Each will activate their respective outputs by loading a logic high.

The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low.

Bypass Register Scan Chain Definition Logic 0

The two least significant bits of this captured value 01 are required by IEEE Std The upper six bits are unique to the SCAN18245T device. SCAN CMOS Test Access Logic devices do not include the IEEE optional identification register. Therefore, this unique captured value can be used as a “pseudo ID” code to confirm that the correct device is placed in the appropriate location in the boundary scan chain.

Instruction Register Scan Chain Definition

MSB LSB Instruction Code

Instruction EXTEST

SAMPLE/PRELOAD

CLAMP

HIGHZ

The INSTRUCTION register is an eight-bit register which captures the value

All Others

BYPASS

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Datasheet ID: SCAN18245TSSC 634702