SCAN182245ASSC

SCAN182245ASSC Datasheet

SCAN182245A Non-Inverting Transceiver with Series Resistor Outputs

Part	Datasheet
SCAN182245ASSC	SCAN182245ASSC (pdf)

Related Parts	Information
SCAN182245ASSCX	SCAN182245ASSCX
SCAN182245AMTDX	SCAN182245AMTDX

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SCAN182245A Non-Inverting Transceiver with Series Resistor Outputs SCAN182245A Non-Inverting Transceiver with Series Resistor Outputs The SCAN182245A is a high performance BiCMOS bidirectional line driver featuring separate data inputs organized into dual 9-bit bytes with byte-oriented output enable and direction control signals. This device is compliant with IEEE Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of Test Data Input TDI , Test Data Out TDO , Test Mode Select TMS , and Test Clock TCK . s High performance BiCMOS technology s series resistors in outputs eliminate the need for external terminating resistors s Dual output enable control signals s 3-STATE outputs for bus-oriented applications s 25 mil pitch SSOP Shrink Small Outline Package s IEEE JTAG Compliant s Includes CLAMP, IDCODE and HIGHZ instructions s Additional instructions SAMPLE-IN, SAMPLE-OUT and EXTEST-OUT s Power Up 3-STATE for hot insert s Member of Fairchild’s SCAN Products Ordering Code: Order Number Package Number Package Description SCAN182245ASSC MS56A 56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide SCAN182245AMTD MTD56 56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names G1, G2 DIR1, DIR2 Description Side A1 Inputs or 3-STATE Outputs Side B1 Inputs or 3-STATE Outputs Side A2 Inputs or 3-STATE Outputs Side B2 Inputs or 3-STATE Outputs Output Enable Pins Active LOW Direction of Data Flow Pins 2001 Fairchild Semiconductor Corporation DS011657 SCAN182245A Truth Tables Inputs Inputs G1 Note 1 DIR1 G2 Note 1 DIR2 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Note 1 Inactive-to-Active transition must occur to enable outputs upon power-up. Functional Description The SCAN182245A consists of two sets of nine non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus-oriented applications. Direction pins DIR1 and DIR2 LOW enables data from B Ports to A Ports, when HIGH enables data from A Ports to B Ports. The Output Enable pins G1 and G2 when HIGH disables both A and B Ports by placing them in a high impedance condition. Block Diagrams A1, B1, G1 and DIR1 A2, B2, G2 and DIR2 Note BSR stands for Boundary Scan Register. Note BSR stands for Boundary Scan Register. Tap Controller SCAN182245A Description of BOUNDARY-SCAN Circuitry The scan cells used in the BOUNDARY-SCAN register are one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system data, while TYPE2 has the additional ability to control system data. Scan cell TYPE1 is located on each system input pin while scan cell TYPE2 is located at each system output pin as well as at each of the two internal active-high output enable signals. AOE controls the activity of the A-outputs while BOE controls the activity of the B-outputs. Each will activate their respective outputs by loading a logic high. The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low. The INSTRUCTION register is an 8-bit register which captures the default value of SAMPLE/PRELOAD during the CAPTURE-IR instruction command. The benefit of capturing SAMPLE/PRELOAD as the default instruction during CAPTURE-IR is that the user is no longer required to shift in the 8-bit instruction for SAMPLE/PRELOAD. The sequence of CAPTURE-IR EXIT1-IR UPDATE-IR will update the SAMPLE/PRELOAD instruction. For more information refer to the section on instruction definitions. Instruction Register Scan Chain Definition Bypass Register Scan Chain Definition Logic 0 SCAN182245A Product IDCODE 32-Bit Code per IEEE Versio n Entity Part Manufacture Required r

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SCAN182245A Non-Inverting Transceiver with Series Resistor Outputs

SCAN182245A

Non-Inverting Transceiver with Series Resistor Outputs

The SCAN182245A is a high performance BiCMOS bidirectional line driver featuring separate data inputs organized into dual 9-bit bytes with byte-oriented output enable and direction control signals. This device is compliant with IEEE Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of Test Data Input TDI , Test Data Out TDO , Test Mode Select TMS , and Test Clock TCK .
s High performance BiCMOS technology s series resistors in outputs eliminate the need for
external terminating resistors s Dual output enable control signals s 3-STATE outputs for bus-oriented applications s 25 mil pitch SSOP Shrink Small Outline Package s IEEE JTAG Compliant s Includes CLAMP, IDCODE and HIGHZ instructions s Additional instructions SAMPLE-IN, SAMPLE-OUT and

EXTEST-OUT s Power Up 3-STATE for hot insert s Member of Fairchild’s SCAN Products
Ordering Code:

Order Number

Package Number

Package Description

SCAN182245ASSC

MS56A
56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide

SCAN182245AMTD

MTD56
56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names

G1, G2

DIR1, DIR2

Description Side A1 Inputs or 3-STATE Outputs Side B1 Inputs or 3-STATE Outputs Side A2 Inputs or 3-STATE Outputs Side B2 Inputs or 3-STATE Outputs Output Enable Pins Active LOW Direction of Data Flow Pins
2001 Fairchild Semiconductor Corporation DS011657

SCAN182245A

Truth Tables

Inputs

Inputs

G1 Note 1

DIR1

G2 Note 1

DIR2

H = HIGH Voltage Level L = LOW Voltage Level

X = Immaterial Z = High Impedance

Note 1 Inactive-to-Active transition must occur to enable outputs upon power-up.

Functional Description

The SCAN182245A consists of two sets of nine non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus-oriented applications. Direction pins DIR1 and DIR2 LOW enables data from B Ports to A Ports,
when HIGH enables data from A Ports to B Ports. The Output Enable pins G1 and G2 when HIGH disables both A and B Ports by placing them in a high impedance condition.

Block Diagrams

A1, B1, G1 and DIR1

A2, B2, G2 and DIR2

Note BSR stands for Boundary Scan Register.

Note BSR stands for Boundary Scan Register.

Tap Controller

SCAN182245A

Description of BOUNDARY-SCAN Circuitry

The scan cells used in the BOUNDARY-SCAN register are one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system data, while TYPE2 has the additional ability to control system data.

Scan cell TYPE1 is located on each system input pin while scan cell TYPE2 is located at each system output pin as well as at each of the two internal active-high output enable signals. AOE controls the activity of the A-outputs while BOE controls the activity of the B-outputs. Each will activate their respective outputs by loading a logic high.

The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low.

The INSTRUCTION register is an 8-bit register which captures the default value of SAMPLE/PRELOAD during the CAPTURE-IR instruction command. The benefit of capturing SAMPLE/PRELOAD as the default instruction during CAPTURE-IR is that the user is no longer required to shift in the 8-bit instruction for SAMPLE/PRELOAD. The sequence of CAPTURE-IR EXIT1-IR UPDATE-IR will update the SAMPLE/PRELOAD instruction. For more information refer to the section on instruction definitions.

Instruction Register Scan Chain Definition

Bypass Register Scan Chain Definition Logic 0

SCAN182245A Product IDCODE 32-Bit Code per IEEE

Versio n

Entity

Part

Manufacture Required r

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived SCAN182245ASSC Datasheet file may be downloaded here without warranties.

Datasheet ID: SCAN182245ASSC 634700