NDS9959

NDS9959 Datasheet

NDS9959 Dual N-Channel Enhancement Mode Field Effect Transistor

Part	Datasheet
NDS9959	NDS9959 (pdf)

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NDS9959 Dual N-Channel Enhancement Mode Field Effect Transistor February 1996 These N-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage applications such as DC motor control and DC/DC conversion where fast switching, low in-line power loss, and resistance to transients are needed. 2.0A, 50V. RDS ON = VGS = 10V High density cell design for extremely low RDS ON . High power and current handling capability in a widely used surface mount package. Dual MOSFET in surface mount package. Absolute Maximum Ratings Symbol Parameter TA = 25°C unless otherwise noted VDSS Drain-Source Voltage VGSS Gate-Source Voltage Drain Current - Continuous TA = 25°C Note 1a - Continuous TA = 70°C Note 1a - Pulsed TA = 25°C Power Dissipation for Dual Operation Power Dissipation for Single Operation Note 1a Note 1b TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS Note 1c Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case Note 1a Note 1 1997 Fairchild Semiconductor Corporation NDS9959 50 ± 20 ± ± ±8 2 1 -55 to 150 78 40 Units V A °C °C/W °C/W NDS9959.SAM Electrical Characteristics TA = 25°C unless otherwise noted Symbol Parameter Conditions OFF CHARACTERISTICS BVDSS IDSS Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current VGS = 0 V, ID = 250 µA VDS = 40 V, VGS = 0 V IGSSF Gate - Body Leakage, Forward

PDF Datasheet Preview

NDS9959 Dual N-Channel Enhancement Mode Field Effect Transistor

February 1996

These N-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage applications such as DC motor control and DC/DC conversion where fast switching, low in-line power loss, and resistance to transients are needed.
2.0A, 50V. RDS ON = VGS = 10V

High density cell design for extremely low RDS ON . High power and current handling capability in a widely used surface mount package. Dual MOSFET in surface mount package.

Absolute Maximum Ratings

Symbol Parameter

TA = 25°C unless otherwise noted

VDSS

Drain-Source Voltage

VGSS

Gate-Source Voltage

Drain Current - Continuous TA = 25°C

Note 1a
- Continuous TA = 70°C

Note 1a
- Pulsed TA = 25°C

Power Dissipation for Dual Operation

Power Dissipation for Single Operation

Note 1a

Note 1b

TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS

Note 1c

Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case

Note 1a Note 1
1997 Fairchild Semiconductor Corporation

NDS9959 50 ± 20 ± ± ±8 2 1
-55 to 150
78 40

Units V A
°C °C/W °C/W

NDS9959.SAM

Electrical Characteristics TA = 25°C unless otherwise noted

Symbol Parameter

Conditions

OFF CHARACTERISTICS

BVDSS IDSS

Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current

VGS = 0 V, ID = 250 µA VDS = 40 V, VGS = 0 V

IGSSF

Gate - Body Leakage, Forward

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Datasheet ID: NDS9959 634635