NDS9405

NDS9405 Datasheet

NDS9405 Single P-Channel Enhancement Mode Field Effect Transistor

Part	Datasheet
NDS9405	NDS9405 (pdf)

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NDS9405 Single P-Channel Enhancement Mode Field Effect Transistor February 1996 These P-Channel enhancement mode power field effect transistors are produced using National's proprietary, high cell density, DMOS technology. This very high density process is been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed. -4.3A, -20V. RDS ON = VGS = -10V High density cell design for extremely low RDS ON High power and current handling capability in a widely used surface mount package. Absolute Maximum Ratings TA = 25°C unless otherwise noted Symbol Parameter VDSS Drain-Source Voltage VGSS Gate-Source Voltage Drain Current - Continuous TA = 25°C Note 1a - Continuous TA = 70°C Note 1a - Pulsed TA = 25°C Maximum Power Dissipation Note 1a Note 1b Note 1c TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case Note 1a Note 1 NDS9405 -20 ± 20 ± ± ± 20 -55 to 150 50 25 Units V A °C °C/W °C/W NDS9405.SAM Electrical Characteristics TA = 25°C unless otherwise noted Symbol Parameter Conditions OFF CHARACTERISTICS BVDSS IDSS Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current VGS = 0 V, ID = -250 µA VDS = -16 V, VGS = 0 V IGSSF Gate - Body Leakage, Forward IGSSR ON CHARACTERISTICS Note 2 VGS th Gate Threshold Voltage VGS = 20 V, VDS = 0 V VGS = -20 V, VDS= 0 V

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NDS9405 Single P-Channel Enhancement Mode Field Effect Transistor

February 1996

These P-Channel enhancement mode power field effect transistors are produced using National's proprietary, high cell density, DMOS technology. This very high density process is been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed.
-4.3A, -20V. RDS ON = VGS = -10V

High density cell design for extremely low RDS ON High power and current handling capability in a widely used surface mount package.

Absolute Maximum Ratings TA = 25°C unless otherwise noted

Symbol Parameter

VDSS

Drain-Source Voltage

VGSS

Gate-Source Voltage

Drain Current - Continuous TA = 25°C Note 1a
- Continuous TA = 70°C Note 1a
- Pulsed

TA = 25°C

Maximum Power Dissipation

Note 1a

Note 1b Note 1c

TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS

Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case

Note 1a Note 1

NDS9405 -20 ± 20 ± ± ± 20
-55 to 150
50 25

Units V A
°C °C/W °C/W

NDS9405.SAM

Electrical Characteristics TA = 25°C unless otherwise noted

Symbol Parameter

Conditions

OFF CHARACTERISTICS

BVDSS IDSS

Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current

VGS = 0 V, ID = -250 µA VDS = -16 V, VGS = 0 V

IGSSF

Gate - Body Leakage, Forward

IGSSR

ON CHARACTERISTICS Note 2

VGS th

Gate Threshold Voltage

VGS = 20 V, VDS = 0 V VGS = -20 V, VDS= 0 V

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Datasheet ID: NDS9405 634622