NDS8961

NDS8961 Datasheet

NDS8961 Dual N-Channel Enhancement Mode Field Effect Transistor

Part	Datasheet
NDS8961	NDS8961 (pdf)

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June 1997 NDS8961 Dual N-Channel Enhancement Mode Field Effect Transistor SO-8 N-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance and provide superior switching performance.These devices are particularly suited for low voltage applications such as DC motor control and DC/DC conversion where fast switching, low in-line power loss, and resistance to transients are needed. A, 30 V. RDS ON = VGS = 10 V RDS ON = VGS = V. High density cell design for extremely low RDS ON . High power and current handling capability in a widely used surface mount package. Dual MOSFET in surface mount package. Absolute Maximum Ratings TA = 25°C unless otherwise noted Symbol Parameter VDSS Drain-Source Voltage VGSS Gate-Source Voltage Drain Current - Continuous - Pulsed Note 1a Power Dissipation for Dual Operation Power Dissipation for Single Operation Note 1a Note 1b Note 1c TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS Thermal Resistance, Junction-to-Ambient Note 1a Thermal Resistance, Junction-to-Case Note 1 1997 Fairchild Semiconductor Corporation NDS8961 30 ±20 10 2 1 -55 to 150 78 40 Units V A W °C °C/W °C/W ELECTRICAL CHARACTERISTICS TA = 25°C unless otherwise noted Symbol Parameter Conditions OFF CHARACTERISTICS BVDSS IDSS Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current VGS = 0 V, ID = 250 µA VDS = 24 V, VGS = 0 V IGSSF Gate - Body Leakage, Forward IGSSR ON CHARACTERISTICS Note 2 VGS th Gate Threshold Voltage VGS = 20 V, VDS = 0 V VGS = -20 V, VDS= 0 V

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June 1997

NDS8961 Dual N-Channel Enhancement Mode Field Effect Transistor

SO-8 N-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance and provide superior switching performance.These devices are particularly suited for low voltage applications such as DC motor control and DC/DC conversion where fast switching, low in-line power loss, and resistance to transients are needed.

A, 30 V. RDS ON = VGS = 10 V RDS ON = VGS = V.

High density cell design for extremely low RDS ON . High power and current handling capability in a widely used surface mount package.

Dual MOSFET in surface mount package.

Absolute Maximum Ratings TA = 25°C unless otherwise noted Symbol Parameter

VDSS

Drain-Source Voltage

VGSS

Gate-Source Voltage

Drain Current - Continuous
- Pulsed

Note 1a

Power Dissipation for Dual Operation

Power Dissipation for Single Operation Note 1a

Note 1b

Note 1c

TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS

Thermal Resistance, Junction-to-Ambient Note 1a

Thermal Resistance, Junction-to-Case Note 1
1997 Fairchild Semiconductor Corporation

NDS8961 30 ±20 10 2 1
-55 to 150
78 40

Units V A W
°C °C/W °C/W

ELECTRICAL CHARACTERISTICS TA = 25°C unless otherwise noted

Symbol Parameter

Conditions

OFF CHARACTERISTICS

BVDSS IDSS

Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current

VGS = 0 V, ID = 250 µA VDS = 24 V, VGS = 0 V

IGSSF

Gate - Body Leakage, Forward

IGSSR

ON CHARACTERISTICS Note 2

VGS th

Gate Threshold Voltage

VGS = 20 V, VDS = 0 V VGS = -20 V, VDS= 0 V

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Datasheet ID: NDS8961 634620