NDS8958

NDS8958 Datasheet

NDS8958 Dual N & P-Channel Enhancement Mode Field Effect Transistor

Part	Datasheet
NDS8958	NDS8958 (pdf)

PDF Datasheet Preview
July 1996 NDS8958 Dual N & P-Channel Enhancement Mode Field Effect Transistor These dual N- and P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance and provide superior switching performance. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed. N-Channel 5.3A, 30V, VGS=10V. P-Channel -4.0A, -30V, VGS=-10V. High density cell design or extremely low RDS ON . High power and current handling capability in a widely used surface mount package. Dual N & P-Channel MOSFET in surface mount package. Absolute Maximum Ratings Symbol Parameter TA= 25°C unless otherwise noted N-Channel VDSS Drain-Source Voltage VGSS Gate-Source Voltage Drain Current - Continuous - Pulsed Note 1a Power Dissipation for Dual Operation Power Dissipation for Single Operation Note 1a Note 1b TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS Note 1c Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case Note 1a Note 1 2 1 -55 to 150 78 40 P-Channel -30 -20 -4 -15 Units V A W °C °C/W °C/W Electrical Characteristics TA = 25°C unless otherwise noted Symbol Parameter Conditions OFF CHARACTERISTICS BVDSS IDSS Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current VGS = 0 V, ID = 250 µA VGS = 0 V, ID = -250 µA VDS = 24 V, VGS = 0 V VDS = -24 V, VGS = 0 V IGSSF Gate - Body Leakage, Forward IGSSR

PDF Datasheet Preview

July 1996

NDS8958 Dual N & P-Channel Enhancement Mode Field Effect Transistor

These dual N- and P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance and provide superior switching performance. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed.

N-Channel 5.3A, 30V, VGS=10V. P-Channel -4.0A, -30V, VGS=-10V.

High density cell design or extremely low RDS ON .

High power and current handling capability in a widely used surface mount package.

Dual N & P-Channel MOSFET in surface mount package.

Absolute Maximum Ratings

Symbol Parameter

TA= 25°C unless otherwise noted N-Channel

VDSS

Drain-Source Voltage

VGSS

Gate-Source Voltage

Drain Current - Continuous
- Pulsed

Note 1a

Power Dissipation for Dual Operation

Power Dissipation for Single Operation

Note 1a

Note 1b

TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS

Note 1c

Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case

Note 1a Note 1
2 1 -55 to 150
78 40

P-Channel -30 -20 -4 -15

Units V A W
°C °C/W °C/W

Electrical Characteristics TA = 25°C unless otherwise noted

Symbol Parameter

Conditions

OFF CHARACTERISTICS

BVDSS IDSS

Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current

VGS = 0 V, ID = 250 µA VGS = 0 V, ID = -250 µA VDS = 24 V, VGS = 0 V

VDS = -24 V, VGS = 0 V

IGSSF

Gate - Body Leakage, Forward

IGSSR

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Datasheet ID: NDS8958 634619