NDS8934

NDS8934 Datasheet

NDS8934 Dual P-Channel Enhancement Mode Field Effect Transistor

Part	Datasheet
NDS8934	NDS8934 (pdf)

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March 1996 NDS8934 Dual P-Channel Enhancement Mode Field Effect Transistor These P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed. -3.8A, -20V. RDS ON = VGS = -4.5V RDS ON = VGS = -2.7V. High density cell design for extremely low RDS ON . High power and current handling capability in a widely used surface mount package. Dual MOSFET in surface mount package. Absolute Maximum Ratings TA = 25°C unless otherwise noted Symbol Parameter VDSS Drain-Source Voltage VGSS Gate-Source Voltage Drain Current - Continuous - Pulsed Note 1a Power Dissipation for Dual Operation Power Dissipation for Single Operation Note 1a Note 1b TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS Note 1c Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case Note 1a Note 1 1997 Fairchild Semiconductor Corporation NDS8934 -20 -8 -15 2 1 -55 to 150 78 40 Units V A W °C °C/W °C/W NDS8934.SAM Electrical Characteristics TA = 25°C unless otherwise noted Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS BVDSS IDSS Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current IGSSF Gate - Body Leakage, Forward IGSSR ON CHARACTERISTICS Note 2

PDF Datasheet Preview

March 1996

NDS8934 Dual P-Channel Enhancement Mode Field Effect Transistor

These P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed.
-3.8A, -20V. RDS ON = VGS = -4.5V RDS ON = VGS = -2.7V.

High density cell design for extremely low RDS ON . High power and current handling capability in a widely used surface mount package.

Dual MOSFET in surface mount package.

Absolute Maximum Ratings TA = 25°C unless otherwise noted

Symbol Parameter

VDSS

Drain-Source Voltage

VGSS

Gate-Source Voltage

Drain Current - Continuous
- Pulsed

Note 1a

Power Dissipation for Dual Operation

Power Dissipation for Single Operation

Note 1a

Note 1b

TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS

Note 1c

Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case

Note 1a Note 1
1997 Fairchild Semiconductor Corporation

NDS8934 -20 -8 -15 2 1
-55 to 150
78 40

Units V A W
°C °C/W °C/W

NDS8934.SAM

Electrical Characteristics TA = 25°C unless otherwise noted

Symbol Parameter

Conditions

Min Typ Max Units

OFF CHARACTERISTICS

BVDSS IDSS

Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current

IGSSF

Gate - Body Leakage, Forward

IGSSR

ON CHARACTERISTICS Note 2

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Datasheet ID: NDS8934 634617