NDS8858H

NDS8858H Datasheet

NDS8858H Complementary MOSFET Half Bridge

Part	Datasheet
NDS8858H	NDS8858H (pdf)

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July 1996 NDS8858H Complementary MOSFET Half Bridge These Complementary MOSFET half bridge devices are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage half bridge applications or CMOS applications when both gates are connected together. N-Channel 6.3A, 30V, VGS=10V. P-Channel -4.8A, -30V, VGS=-10V. High density cell design or extremely low RDS ON . High power and current handling capability in a widely used surface mount package. Matched pair for equal input capacitance and power capability P-Gate N -Gate V+ Vout Absolute Maximum Ratings TA= 25°C unless otherwise noted Symbol Parameter N-Channel VDSS Drain-Source Voltage VGSS Gate-Source Voltage Drain Current - Continuous Note 1a &2 - Pulsed Maximum Power Dissipation Single Device Note 1a Note 1b Note 1c TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS Thermal Resistance, Junction-to-Ambient Single Device Note 1a Thermal Resistance, Junction-to-Case Single Device Note 1a 1 -55 to 150 P-Channel -30 -20 Units V A °C/W °C/W 1997 Fairchild Semiconductor Corporation Electrical Characteristics TA = 25°C unless otherwise noted Symbol Parameter Conditions OFF CHARACTERISTICS BVDSS IDSS Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current VGS = 0 V, ID = 250 µA VGS = 0 V, ID = -250 µA VDS = 24 V, VGS = 0 V

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July 1996

NDS8858H Complementary MOSFET Half Bridge

These Complementary MOSFET half bridge devices are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage half bridge applications or CMOS applications when both gates are connected together.

N-Channel 6.3A, 30V, VGS=10V. P-Channel -4.8A, -30V, VGS=-10V.

High density cell design or extremely low RDS ON . High power and current handling capability in a widely used surface mount package.

Matched pair for equal input capacitance and power capability

P-Gate N -Gate

V+ Vout

Absolute Maximum Ratings TA= 25°C unless otherwise noted

Symbol Parameter

N-Channel

VDSS

Drain-Source Voltage

VGSS

Gate-Source Voltage

Drain Current - Continuous

Note 1a &2
- Pulsed

Maximum Power Dissipation

Single Device

Note 1a Note 1b

Note 1c

TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS

Thermal Resistance, Junction-to-Ambient

Single Device

Note 1a

Thermal Resistance, Junction-to-Case

Single Device

Note 1a
1 -55 to 150

P-Channel -30 -20

Units V A
°C/W °C/W
1997 Fairchild Semiconductor Corporation

Electrical Characteristics TA = 25°C unless otherwise noted

Symbol Parameter

Conditions

OFF CHARACTERISTICS

BVDSS IDSS

Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current

VGS = 0 V, ID = 250 µA VGS = 0 V, ID = -250 µA VDS = 24 V, VGS = 0 V

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Datasheet ID: NDS8858H 634615