NDS355N

NDS355N Datasheet

NDS355N N-Channel Logic Level Enhancement Mode Field Effect Transistor

Part	Datasheet
NDS355N	NDS355N (pdf)

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March 1996 NDS355N N-Channel Logic Level Enhancement Mode Field Effect Transistor These N-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications in notebook computers, portable phones, PCMICA cards, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package. 1.6A, 30V. RDS ON = VGS = 4.5V. Proprietary package design using copper lead frame for superior thermal and electrical capabilities. High density cell design for extremely low RDS ON . Exceptional on-resistance and maximum DC current capability. Compact industry standard SOT-23 surface mount package. Absolute Maximum Ratings Symbol Parameter TA = 25°C unless otherwise noted VDSS Drain-Source Voltage VGSS Gate-Source Voltage - Continuous Drain Current - Continuous - Pulsed Note 1a Maximum Power Dissipation Note 1a Note 1b TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS Thermal Resistance, Junction-to-Ambient Note 1a Thermal Resistance, Junction-to -Case Note 1 1997 Fairchild Semiconductor Corporation NDS355N 30 20 ± ± 10 -55 to 150 250 75 Units V A W °C °C/W °C/W Electrical Characteristics TA = 25°C unless otherwise noted Symbol Parameter Conditions OFF CHARACTERISTICS BVDSS IDSS Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current VGS = 0 V, ID = 250 µA VDS = 24 V, VGS = 0 V IGSSF Gate - Body Leakage, Forward IGSSR ON CHARACTERISTICS Note 2 VGS th

PDF Datasheet Preview

March 1996

NDS355N N-Channel Logic Level Enhancement Mode Field Effect Transistor

These N-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications in notebook computers, portable phones, PCMICA cards, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package.
1.6A, 30V. RDS ON = VGS = 4.5V.

Proprietary package design using copper lead frame for superior thermal and electrical capabilities.

High density cell design for extremely low RDS ON .

Exceptional on-resistance and maximum DC current capability.

Compact industry standard SOT-23 surface mount package.

Absolute Maximum Ratings

Symbol Parameter

TA = 25°C unless otherwise noted

VDSS

Drain-Source Voltage

VGSS

Gate-Source Voltage - Continuous

Drain Current - Continuous
- Pulsed

Note 1a

Maximum Power Dissipation

Note 1a

Note 1b

TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS

Thermal Resistance, Junction-to-Ambient Note 1a Thermal Resistance, Junction-to -Case Note 1
1997 Fairchild Semiconductor Corporation

NDS355N 30 20 ± ± 10
-55 to 150
250 75

Units V A W °C
°C/W °C/W

Electrical Characteristics TA = 25°C unless otherwise noted

Symbol Parameter

Conditions

OFF CHARACTERISTICS

BVDSS IDSS

Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current

VGS = 0 V, ID = 250 µA VDS = 24 V, VGS = 0 V

IGSSF

Gate - Body Leakage, Forward

IGSSR

ON CHARACTERISTICS Note 2

VGS th

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Datasheet ID: NDS355N 634606