NDS352P

NDS352P Datasheet

NDS352P P-Channel Logic Level Enhancement Mode Field Effect Transistor

Part	Datasheet
NDS352P	NDS352P (pdf)

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March 1996 NDS352P P-Channel Logic Level Enhancement Mode Field Effect Transistor These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as notebook computer power management, portable electronics, and other battery powered circuits where fast high-side switching, and low in-line power loss are needed in a very small outline surface mount package. -0.85A, -20V. RDS ON = VGS = -4.5V. Proprietary package design using copper lead frame for superior thermal and electrical capabilities. High density cell design for extremely low RDS ON . Exceptional on-resistance and maximum DC current capability. Compact industry standard SOT-23 surface mount package. Absolute Maximum Ratings Symbol Parameter TA = 25°C unless otherwise noted VDSS Drain-Source Voltage VGSS Gate-Source Voltage - Continuous Maximum Drain Current - Continuous - Pulsed Maximum Power Dissipation Note 1a Note 1a Note 1b TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case Note 1a Note 1 NDS352P -20 ±12 ±10 -55 to 150 1997 Fairchild Semiconductor Corporation Units V A W °C °C/W °C/W Electrical Characteristics TA = 25°C unless otherwise noted Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS BVDSS IDSS Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current IGSSF Gate - Body Leakage, Forward IGSSR ON CHARACTERISTICS Note 2 VGS = 0 V, ID = -250 µA VDS = -16 V, VGS = 0 V VGS = 12 V, VDS = 0 V VGS = -12 V, VDS = 0 V

PDF Datasheet Preview

March 1996

NDS352P P-Channel Logic Level Enhancement Mode Field Effect Transistor

These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as notebook computer power management, portable electronics, and other battery powered circuits where fast high-side switching, and low in-line power loss are needed in a very small outline surface mount package.
-0.85A, -20V. RDS ON = VGS = -4.5V.

Proprietary package design using copper lead frame for superior thermal and electrical capabilities.

High density cell design for extremely low RDS ON .

Exceptional on-resistance and maximum DC current capability.

Compact industry standard SOT-23 surface mount package.

Absolute Maximum Ratings

Symbol Parameter

TA = 25°C unless otherwise noted

VDSS

Drain-Source Voltage

VGSS

Gate-Source Voltage - Continuous

Maximum Drain Current - Continuous
- Pulsed

Maximum Power Dissipation

Note 1a

Note 1a Note 1b

TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS

Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case

Note 1a Note 1

NDS352P -20 ±12 ±10
-55 to 150
1997 Fairchild Semiconductor Corporation

Units V A W °C
°C/W °C/W

Electrical Characteristics TA = 25°C unless otherwise noted

Symbol Parameter

Conditions

Min Typ Max Units

OFF CHARACTERISTICS

BVDSS IDSS

Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current

IGSSF

Gate - Body Leakage, Forward

IGSSR

ON CHARACTERISTICS Note 2

VGS = 0 V, ID = -250 µA VDS = -16 V, VGS = 0 V

VGS = 12 V, VDS = 0 V VGS = -12 V, VDS = 0 V

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Datasheet ID: NDS352P 634605