NDS336P

NDS336P Datasheet

NDS336P P-Channel Logic Level Enhancement Mode Field Effect Transistor

Part	Datasheet
NDS336P	NDS336P (pdf)

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June 1997 NDS336P P-Channel Logic Level Enhancement Mode Field Effect Transistor SuperSOTTM-3 P-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as notebook computer power management, portable electronics, and other battery powered circuits where fast high-side switching, and low in-line power loss are needed in a very small outline surface mount package. A, -20 V, RDS ON = VGS= V RDS ON = VGS = V. Very low level gate drive requirements allowing direct operation in 3V circuits. VGS th < 1.0V. Proprietary package design using copper lead frame for superior thermal and electrical capabilities. High density cell design for extremely low RDS ON . Exceptional on-resistance and maximum DC current capability. Compact industry standard SOT-23 surface Mount package. Absolute Maximum Ratings TA = 25°C unless otherwise noted Symbol Parameter VDSS Drain-Source Voltage VGSS Gate-Source Voltage - Continuous Maximum Drain Current - Continuous - Pulsed Note 1a Maximum Power Dissipation Note 1a Note 1b TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS Thermal Resistance, Junction-to-Ambient Note 1a Thermal Resistance, Junction-to-Case Note 1 1997 Fairchild Semiconductor Corporation NDS336P -20 ±8 -10 -55 to 150 250 75 Units V A °C/W °C/W Electrical Characteristics TA = 25°C unless otherwise noted Symbol Parameter Conditions OFF CHARACTERISTICS BVDSS IDSS Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current VGS = 0 V, ID = -250 µA VDS = -16 V, VGS = 0 V IGSS Gate - Body Leakage Current IGSS Gate - Body Leakage Current

PDF Datasheet Preview

June 1997

NDS336P P-Channel Logic Level Enhancement Mode Field Effect Transistor

SuperSOTTM-3 P-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as notebook computer power management, portable electronics, and other battery powered circuits where fast high-side switching, and low in-line power loss are needed in a very small outline surface mount package.

A, -20 V, RDS ON = VGS= V RDS ON = VGS = V.

Very low level gate drive requirements allowing direct operation in 3V circuits. VGS th < 1.0V.

Proprietary package design using copper lead frame for superior thermal and electrical capabilities.

High density cell design for extremely low RDS ON .

Exceptional on-resistance and maximum DC current capability.

Compact industry standard SOT-23 surface Mount package.

Absolute Maximum Ratings TA = 25°C unless otherwise noted

Symbol Parameter

VDSS

Drain-Source Voltage

VGSS

Gate-Source Voltage - Continuous

Maximum Drain Current - Continuous
- Pulsed

Note 1a

Maximum Power Dissipation

Note 1a Note 1b

TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS

Thermal Resistance, Junction-to-Ambient Note 1a

Thermal Resistance, Junction-to-Case

Note 1
1997 Fairchild Semiconductor Corporation

NDS336P -20 ±8 -10
-55 to 150
250 75

Units V A
°C/W °C/W

Electrical Characteristics TA = 25°C unless otherwise noted

Symbol Parameter

Conditions

OFF CHARACTERISTICS

BVDSS IDSS

Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current

VGS = 0 V, ID = -250 µA VDS = -16 V, VGS = 0 V

IGSS

Gate - Body Leakage Current

IGSS

Gate - Body Leakage Current

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Datasheet ID: NDS336P 634604