MM74HC589N

MM74HC589N Datasheet

MM74HC589 8-Bit Shift Registers with Input Latches and 3-STATE Serial Output

Part	Datasheet
MM74HC589N	MM74HC589N (pdf)

Related Parts	Information
MM74HC589M	MM74HC589M
MM74HC589SJ	MM74HC589SJ
MM74HC589SJX	MM74HC589SJX
MM74HC589MX	MM74HC589MX

PDF Datasheet Preview
MM74HC589 8-Bit Shift Registers with Input Latches and 3-STATE Serial Output MM74HC589 8-Bit Shift Registers with Input Latches and 3-STATE Serial Output The MM74HC589 high speed shift register utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads. The MM74HC589 comes in a 16-pin package and consists of an 8-bit storage latch feeding a parallel-in, serial-out 8bit shift register. Data can also be entered serially the shift register through the SER pin. Both the storage register and shift register have positive-edge triggered clocks, RCK and SCK, respectively. SLOAD pin controls parallel LOAD or serial shift operations for the shift register. The shift register has a 3-STATE output to enable the wire-ORing of multiple devices on a serial bus. The 74HC logic family is speed, function, and pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. s 8-bit parallel storage register inputs s Wide operating voltage range s Shift register has direct overriding load s Guaranteed shift frequency. DC to 30 MHz s Low quiescent current 80 µA maximum 74HC Series s 3-STATE output for ‘Wire-OR' Ordering Code: Order Number Package Number Package Description MM74HC589M M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow MM74HC589SJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide MM74HC589N N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table Top View RCK SCK SLOAD OE Function H QH in Hi-Z State L QH is enabled X Data loaded into input latches L X Data loaded into shift register from pins H or L X L X Data loaded from latches to shift register H X Shift register is shifted. Data on SER pin is shifted in. H X Data is shifted in shift register, and data is loaded into latches 2001 Fairchild Semiconductor Corporation DS005368 MM74HC589 Block Diagram positive logic MM74HC589 Absolute Maximum Ratings Note 1 Note 2 Supply Voltage VCC DC Input Voltage VIN DC Output Voltage VOUT Clamp Diode Current IIK, IOK DC Output Current, per pin IOUT DC VCC or GND Current, per pin ICC Storage Temperature Range TSTG Power Dissipation PD Note 3 S.O. Package only Lead Temperature TL Soldering 10 seconds to +7.0V to VCC +1.5V to VCC +0.5V ±20 mA ±25 mA ±50 mA −65°C to +150°C 600 mW 500 mW 260°C Recommended Operating Conditions Min Max Units Supply Voltage VCC DC Input or Output Voltage VIN, VOUT Operating Temperature Range TA −40 +85 °C Input Rise or Fall Times tr, tf VCC = 2.0V 1000 ns VCC = 4.5V

PDF Datasheet Preview

MM74HC589 8-Bit Shift Registers with Input Latches and 3-STATE Serial Output

MM74HC589 8-Bit Shift Registers with Input Latches and 3-STATE Serial Output

The MM74HC589 high speed shift register utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads.

The MM74HC589 comes in a 16-pin package and consists of an 8-bit storage latch feeding a parallel-in, serial-out 8bit shift register. Data can also be entered serially the shift register through the SER pin. Both the storage register and shift register have positive-edge triggered clocks, RCK and SCK, respectively. SLOAD pin controls parallel LOAD or serial shift operations for the shift register. The shift register has a 3-STATE output to enable the wire-ORing of multiple devices on a serial bus.

The 74HC logic family is speed, function, and pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.
s 8-bit parallel storage register inputs s Wide operating voltage range s Shift register has direct overriding load s Guaranteed shift frequency. DC to 30 MHz s Low quiescent current 80 µA maximum 74HC Series s 3-STATE output for ‘Wire-OR'
Ordering Code:

Order Number Package Number

Package Description

MM74HC589M

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow

MM74HC589SJ

M16D
16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide

MM74HC589N

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Truth Table

Top View

RCK SCK SLOAD OE

Function

H QH in Hi-Z State

L QH is enabled

X Data loaded into input latches

L X Data loaded into shift register
from pins

H or L X

L X Data loaded from latches to
shift register

H X Shift register is shifted. Data
on SER pin is shifted in.

H X Data is shifted in shift register,
and data is loaded into latches
2001 Fairchild Semiconductor Corporation DS005368

MM74HC589

Block Diagram positive logic

MM74HC589

Absolute Maximum Ratings Note 1

Note 2

Supply Voltage VCC DC Input Voltage VIN DC Output Voltage VOUT Clamp Diode Current IIK, IOK DC Output Current, per pin IOUT DC VCC or GND Current, per pin ICC Storage Temperature Range TSTG Power Dissipation PD

Note 3

S.O. Package only

Lead Temperature TL Soldering 10 seconds
to +7.0V to VCC +1.5V to VCC +0.5V
±20 mA ±25 mA ±50 mA −65°C to +150°C
600 mW 500 mW
260°C

Recommended Operating Conditions

Min Max Units

Supply Voltage VCC DC Input or Output Voltage

VIN, VOUT

Operating Temperature Range TA −40 +85 °C

Input Rise or Fall Times
tr, tf VCC = 2.0V
1000 ns

VCC = 4.5V

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Datasheet ID: MM74HC589N 634393