MM74HC259MTC

MM74HC259MTC Datasheet

MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder

Part	Datasheet
MM74HC259MTC	MM74HC259MTC (pdf)

Related Parts	Information
MM74HC259MX	MM74HC259MX
MM74HC259SJX	MM74HC259SJX
MM74HC259SJ	MM74HC259SJ
MM74HC259MTCX	MM74HC259MTCX
MM74HC259N	MM74HC259N
MM74HC259M	MM74HC259M

PDF Datasheet Preview
MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder The MM74HC259 device utilizes advanced silicon-gate CMOS technology to implement an 8-bit addressable latch, designed for general purpose storage applications in digital systems. The MM74HC259 has a single data input D , 8 latch outputs 3 address inputs A, B, and C , a common enable input G , and a common CLEAR input. To operate this device as an addressable latch, data is held on the D input, and the address of the latch into which the data is to be entered is held on the A, B, and C inputs. When ENABLE is taken LOW the data flows through to the addressed output. The data is stored when ENABLE transitions from LOW-to-HIGH. All unaddressed latches will remain unaffected. With enable in the HIGH state the device is deselected, and all latches remain in their previous state, unaffected by changes on the data or address inputs. To eliminate the possibility of entering erroneous data into the latches, the enable should be held HIGH inactive while the address lines are changing. If enable is held HIGH and CLEAR is taken LOW all eight latches are cleared to a LOW state. If enable is LOW all latches except the addressed latch will be cleared. The addressed latch will instead follow the D input, effectively implementing a 3-to-8 line decoder. All inputs are protected from damage due to static discharge by diodes to VCC and ground. s Typical propagation delay 18 ns s Wide supply range s Low input current 1 µA maximum s Low quiescent current 80 µA maximum 74HC Series Ordering Code: Order Number Package Number Package Description MM74HC259M M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, Narrow MM74HC259SJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide MM74HC259MTC MTC16 16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide MM74HC259N N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Latch Selection Table Pin Assignments for DIP, SOIC, SOP and TSSOP Top View Select Inputs H = HIGH level, L = LOW level D = the level at the data input Qi0 the level of Qi i = 0, 1 as appropriate before the indicated steady-state input conditions were established. Latch Addressed 0 1 2 3 4 5 6 7 1999 Fairchild Semiconductor Corporation DS005006.prf MM74HC259 Truth Table Inputs Clear G Outputs of Addressed Latch D Qi0 D L Each Other Output Qi0 L Function Addressable Latch Memory 8-Line Decoder Clear Logic Diagram MM74HC259 Absolute Maximum Ratings Note 1 Note 2 Recommended Operating Conditions Supply Voltage VCC DC Input Voltage VIN DC Output Voltage VOUT Clamp Diode Current IIK, IOK DC Output Current, per pin IOUT DC VCC or GND Current, per pin ICC Storage Temperature Range TSTG Power Dissipation PD Note 3 S.O. Package only Lead Temperature TL Soldering 10 seconds to +7.0V to VCC+1.5V to VCC+0.5V ±20 mA ±25 mA ±50 mA −65°C to +150°C 600 mW 500 mW 260°C Min Max Units Supply Voltage VCC DC Input or Output Voltage VIN, VOUT Operating Temperature Range TA −40 +85 °C Input Rise or Fall Times tr, tf VCC = 2.0V

PDF Datasheet Preview

MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder

MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder

The MM74HC259 device utilizes advanced silicon-gate CMOS technology to implement an 8-bit addressable latch, designed for general purpose storage applications in digital systems.

The MM74HC259 has a single data input D , 8 latch outputs 3 address inputs A, B, and C , a common enable input G , and a common CLEAR input. To operate this device as an addressable latch, data is held on the D input, and the address of the latch into which the data is to be entered is held on the A, B, and C inputs. When ENABLE is taken LOW the data flows through to the addressed output. The data is stored when ENABLE transitions from LOW-to-HIGH. All unaddressed latches will remain unaffected. With enable in the HIGH state the device is deselected, and all latches remain in their previous state, unaffected by changes on the data or address
inputs. To eliminate the possibility of entering erroneous data into the latches, the enable should be held HIGH inactive while the address lines are changing.

If enable is held HIGH and CLEAR is taken LOW all eight latches are cleared to a LOW state. If enable is LOW all latches except the addressed latch will be cleared. The addressed latch will instead follow the D input, effectively implementing a 3-to-8 line decoder.

All inputs are protected from damage due to static discharge by diodes to VCC and ground.
s Typical propagation delay 18 ns s Wide supply range s Low input current 1 µA maximum s Low quiescent current 80 µA maximum 74HC Series
Ordering Code:

Order Number Package Number Package Description

MM74HC259M

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, Narrow

MM74HC259SJ

M16D
16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide

MM74HC259MTC

MTC16
16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide

MM74HC259N

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Latch Selection Table

Pin Assignments for DIP, SOIC, SOP and TSSOP Top View

Select Inputs

H = HIGH level, L = LOW level D = the level at the data input Qi0 the level of Qi i = 0, 1 as appropriate before the indicated steady-state input
conditions were established.

Latch Addressed
0 1 2 3 4 5 6 7
1999 Fairchild Semiconductor Corporation DS005006.prf

MM74HC259

Truth Table

Inputs

Clear G

Outputs of Addressed

Latch D Qi0 D L

Each Other Output

Qi0 L

Function

Addressable Latch Memory
8-Line Decoder Clear

Logic Diagram

MM74HC259

Absolute Maximum Ratings Note 1

Note 2

Recommended Operating Conditions

Supply Voltage VCC DC Input Voltage VIN DC Output Voltage VOUT Clamp Diode Current IIK, IOK DC Output Current, per pin IOUT DC VCC or GND Current, per pin ICC Storage Temperature Range TSTG Power Dissipation PD

Note 3

S.O. Package only

Lead Temperature TL Soldering 10 seconds
to +7.0V to VCC+1.5V to VCC+0.5V
±20 mA ±25 mA ±50 mA −65°C to +150°C
600 mW 500 mW
260°C

Min Max Units

Supply Voltage VCC

DC Input or Output Voltage

VIN, VOUT

Operating Temperature Range TA −40 +85 °C

Input Rise or Fall Times
tr, tf VCC = 2.0V

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Datasheet ID: MM74HC259MTC 634380