MM74HC174MTC
MM74HC174MTC Datasheet
MM74HC174 Hex D-Type Flip-Flops with Clear
| Part | Datasheet |
|---|---|
MM74HC174MTC |
MM74HC174MTC (pdf) |
| Related Parts | Information |
|---|---|
MM74HC174N |
MM74HC174N |
|
MM74HC174M |
MM74HC174M |
MM74HC174SJ |
MM74HC174SJ |
|
MM74HC174MX |
MM74HC174MX |
MM74HC174SJX |
MM74HC174SJX |
|
MM74HC174MTCX |
MM74HC174MTCX |
| PDF Datasheet Preview |
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| MM74HC174 Hex D-Type Flip-Flops with Clear MM74HC174 Hex D-Type Flip-Flops with Clear The MM74HC174 edge triggered flip-flops utilize advanced silicon-gate CMOS technology to implement D-type flipflops. They possess high noise immunity, low power, and speeds comparable to low power Schottky TTL circuits. This device contains 6 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the LOW-to-HIGH transition of the CLOCK input. The CLEAR input when LOW, sets all outputs to a low state. Each output can drive 10 low power Schottky TTL equivalent loads. The MM74HC174 is functionally as well as pin compatible to the 74LS174. All inputs are protected from damage due to static discharge by diodes to VCC and ground. s Typical propagation delay 16 ns s Wide operating voltage range s Low input current 1 µA maximum s Low quiescent current 80 µA 74HC Series s Output drive 10 LSTTL loads Ordering Code: Order Number Package Number Package Description MM74HC174M M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow MM74HC174SJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide MM74HC174MTC MTC16 16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide MM74HC174N N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP Truth Table Each Flip-Flop Inputs Clear Clock D Outputs Q L H L Q0 H = HIGH Level steady state L = LOW Level steady state X = Don't Care = Transition from LOW-to-HIGH level Q0 = The level of Q before the indicated steady state input conditions were established. 1999 Fairchild Semiconductor Corporation DS005318.prf MM74HC174 Logic Diagram MM74HC174 Absolute Maximum Ratings Note 1 Note 2 Supply Voltage VCC DC Input Voltage VIN DC Output Voltage VOUT Clamp Diode Current IIK, IOK DC Output Current, per pin IOUT DC VCC or GND Current, per pin ICC Storage Temperature Range TSTG Power Dissipation PD Note 3 S.O. Package only Lead Temperature TL Soldering 10 seconds to +7.0V to VCC +1.5V to VCC +0.5V ±20 mA ±25 mA ±50 mA −65°C to +150°C 600 mW 500 mW 260°C Recommended Operating Conditions Min Max Units Supply Voltage VCC DC Input or Output Voltage VIN, VOUT 0 VCC V Operating Temperature Range TA −40 +85 °C Input Rise or Fall Times tr, tf VCC = 2.0V 1000 ns VCC = 4.5V 500 ns VCC = 6.0V 400 ns Note 1 Absolute Maximum Ratings are those values beyond which dam- age to the device may occur. Note 2 Unless otherwise specified all voltages are referenced to ground. Note 3 Power Dissipation temperature derating plastic “N” package − 12 mW/°C from 65°C to 85°C. DC Electrical Characteristics Note 4 |
| More datasheets: 2S09-05.0 | 2SS09-08.0 | 2SS09-10.0 | 2SS09-09.0 | 2SS09-07.0 | 2S09-08.0 | MM74HC174N | MM74HC174M | MM74HC174SJ | MM74HC174MX |
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