MM74C76N

MM74C76N Datasheet

MM74C73<br>• MM74C76 Dual J-K Flip-Flops with Clear and Preset

Part	Datasheet
MM74C76N	MM74C76N (pdf)

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MM74C73 • MM74C76 Dual J-K Flip-Flops with Clear and Preset MM74C73 • MM74C76 Dual J-K Flip-Flops with Clear and Preset The MM74C73 and MM74C76 dual J-K flip-flops are monolithic complementary MOS CMOS integrated circuits constructed with N- and P-channel enhancement transistors. Each flip-flop has independent J, K, clock and clear inputs and Q and Q outputs. The MM74C76 flip flops also include preset inputs and are supplied in 16 pin packages. This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Clear or preset is independent of the clock and is accomplished by a low level on the respective input. s Supply voltage range 3V to 15V s Tenth power TTL compatible Drive 2 LPTTL loads s High noise immunity VCC typ. s Low power 50 nW typ. s Medium speed operation 10 MHz typ. • Automotive • Data terminals • Instrumentation • Medical electronics • Alarm systems • Industrial electronics • Remote metering • Computers Ordering Code: Order Number Package Number Package Description MM74C73N N14A 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide MM74C76M M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow MM74C76N N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagrams MM74C73 MM74C76 Note A logic “0” on clear sets Q to logic Top View Note A logic “0” on clear sets Q to a logic Note A logic “0” on preset sets Q to a logic Top View 2002 Fairchild Semiconductor Corporation DS005884 MM74C73 • MM74C76 Truth Table tn = bit time before clock pulse tn+1 = bit time after clock pulse Logic Diagrams tn+1 Preset Clear Note 1 Note 1 Note 1 No change in output from previous state MM74C73 MM74C76 Transmission Gate MM74C73 • MM74C76 Absolute Maximum Ratings Note 2 Voltage at Any Pin Operating Temperature Range Storage Temperature Power Dissipation Dual-In-Line Small Outline Lead Temperature Soldering, 10 seconds Operating VCC Range VCC Max −0.3V to VCC + 0.3V −55°C to +125°C −65°C to +150°C 700 mW 500 mW 260°C +3V to 15V Note 2 “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of Electrical Characteristics provides conditions for actual device operation. DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted Parameter Conditions CMOS TO CMOS VIN 1 Logical “1” Input Voltage VIN 0 Logical “0” Input Voltage VOUT 1 Logical “1” Output Voltage

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MM74C73
• MM74C76 Dual J-K Flip-Flops with Clear and Preset

MM74C73
• MM74C76 Dual J-K Flip-Flops with Clear and Preset

The MM74C73 and MM74C76 dual J-K flip-flops are monolithic complementary MOS CMOS integrated circuits constructed with N- and P-channel enhancement transistors. Each flip-flop has independent J, K, clock and clear inputs and Q and Q outputs. The MM74C76 flip flops also include preset inputs and are supplied in 16 pin packages. This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Clear or preset is independent of the clock and is accomplished by a low level on the respective input.
s Supply voltage range 3V to 15V s Tenth power TTL compatible Drive 2 LPTTL loads s High noise immunity VCC typ. s Low power 50 nW typ. s Medium speed operation 10 MHz typ.
• Automotive
• Data terminals
• Instrumentation
• Medical electronics
• Alarm systems
• Industrial electronics
• Remote metering
• Computers
Ordering Code:

Order Number Package Number

Package Description

MM74C73N

N14A
14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide

MM74C76M

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow

MM74C76N

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagrams

MM74C73

MM74C76

Note A logic “0” on clear sets Q to logic

Top View

Note A logic “0” on clear sets Q to a logic Note A logic “0” on preset sets Q to a logic

Top View
2002 Fairchild Semiconductor Corporation DS005884

MM74C73
• MM74C76

Truth Table
tn = bit time before clock pulse tn+1 = bit time after clock pulse

Logic Diagrams
tn+1

Preset

Clear

Note 1

Note 1

Note 1 No change in output from previous state

MM74C73

MM74C76

Transmission Gate

MM74C73
• MM74C76

Absolute Maximum Ratings Note 2

Voltage at Any Pin Operating Temperature Range Storage Temperature Power Dissipation

Dual-In-Line Small Outline Lead Temperature Soldering, 10 seconds Operating VCC Range VCC Max
−0.3V to VCC + 0.3V −55°C to +125°C −65°C to +150°C
700 mW 500 mW
260°C +3V to 15V

Note 2 “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of Electrical Characteristics provides conditions for actual device operation.

DC Electrical Characteristics

Min/Max limits apply across temperature range unless otherwise noted

Parameter

Conditions

CMOS TO CMOS

VIN 1

Logical “1” Input Voltage

VIN 0

Logical “0” Input Voltage

VOUT 1

Logical “1” Output Voltage

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Datasheet ID: MM74C76N 634356