MM74C373N
MM74C373N Datasheet
MM74C373<br>• MM74C374 3-STATE Octal D-Type Latch<br>• 3-STATE Octal D-Type Flip-Flop
| Part | Datasheet |
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MM74C373N |
MM74C373N (pdf) |
| Related Parts | Information |
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MM74C374N |
MM74C374N |
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MM74C374WM |
MM74C374WM |
| PDF Datasheet Preview |
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| MM74C373 • MM74C374 3-STATE Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop MM74C373 • MM74C374 3-STATE Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop The MM74C373 and MM74C374 are integrated, complementary MOS CMOS , 8-bit storage elements with 3STATE outputs. These outputs have been specially designed to drive high capacitive loads, such as one might find when driving a bus, and to have a fan out of 1 when driving standard TTL. When a high logic level is applied to the OUTPUT DISABLE input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The MM74C373 is an 8-bit latch. When LATCH ENABLE is high, the Q outputs will follow the D inputs. When LATCH ENABLE goes low, data at the D inputs, which meets the set-up and hold time requirements, will be retained at the outputs until LATCH ENABLE returns high again. The MM74C374 is an 8-bit, D-type, positive-edge triggered flip-flop. Data at the D inputs, meeting the set-up and hold time requirements, is transferred to the Q outputs on positive-going transitions of the CLOCK input. Both the MM74C373 and the MM74C374 are being assembled in 20-pin dual-in-line packages with pin centers. s Wide supply voltage range 3V to 15V s High noise immunity VCC typ. s Low power consumption s TTL compatibility: Fan out of 1driving standard TTL s Bus driving capability s 3-STATE outputs s Eight storage elements in one package s Single CLOCK/LATCH ENABLE and OUTPUT DIS- ABLE control inputs s 20-pin dual-in-line package with centers takes half the board space of a 24-pin package Ordering Code: Order Number Package Number Package Description MM74C373M Note 1 M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide MM74C373N N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide MM74C374N N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Note 1 Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. 2004 Fairchild Semiconductor Corporation DS005906 MM74C373 • MM74C374 Connection Diagrams MM74C373 MM74C374 Top View Truth Tables MM74C373 Output LATCH Disable ENABLE L = LOW logic level H = HIGH logic level X = Irrelevant Top View H L Q Hi-Z MM74C374 Output Clock Disable = LOW-to-HIGH logic level transition Q = Preexisting output level Hi-Z = High impedance output state H L Q Hi-Z MM74C373 • MM74C374 Block Diagrams MM74C373 1 of 8 Latches MM74C374 1 of 8 Flip-Flops MM74C373 • MM74C374 Absolute Maximum Ratings Note 2 Voltage at Any Pin Operating Temperature Range TA MM74C373 Storage Temperature Range TS Power Dissipation Dual-In-Line Small Outline Operating VCC Range Absolute Maximum VCC Lead Temperature TL Soldering, 10 seconds −0.3V to VCC + 0.3V −55°C to +125°C −65°C to +150°C 700 mW 500 mW 3V to 15V 260°C Note 2 “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted Parameter |
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