GTLP18T612MTD

GTLP18T612MTD Datasheet

GTLP18T612 18-Bit LVTTL/GTLP Universal Bus Transceiver

Part	Datasheet
GTLP18T612MTD	GTLP18T612MTD (pdf)

Related Parts	Information
GTLP18T612MEAX	GTLP18T612MEAX
GTLP18T612MTDX	GTLP18T612MTDX
GTLP18T612MEA	GTLP18T612MEA

PDF Datasheet Preview
GTLP18T612 18-Bit LVTTL/GTLP Universal Bus Transceiver GTLP18T612 18-Bit LVTTL/GTLP Universal Bus Transceiver The GTLP18T612 is an 18-bit universal bus transceiver which provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed interface for cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP’s reduced output swing < 1V , reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic GTL JEDEC standard JESD8-3. Fairchild’s GTLP has internal edge-rate control and is Process, Voltage, and Temperature PVT compensated. Its function is similar to BTL or GTL but with different output levels and receiver thresholds. GTLP output LOW level is less than 0.5V, the output HIGH is 1.5V and the receiver threshold is 1.0V. s Bidirectional interface between GTLP and LVTTL logic levels s Designed with edge rate control circuitry to reduce output noise on the GTLP port s VREF pin provides external supply reference voltage for receiver threshold adjustibility s Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature s TTL compatible driver and control inputs s Designed using Fairchild advanced BiCMOS technology s Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs s Power up/down and power off high impedance for live insertion s Open drain on GTLP to support wired-or connection s Flow through pinout optimizes PCB layout s D-type flip-flop, latch and transparent data paths s A Port source/sink −24mA/+24mA s B Port sink +50mA s Also packaged in plastic Fine-Pitch Ball Grid Array FBGA Ordering Code: Order Number Package Number Package Description GTLP18T612G Note 1 Note 2 BGA54A 54-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide GTLP18T612MEA Note 2 MS56A 56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide GTLP18T612MTD Note 2 MTD56 56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Note 1 Ordering code “G” indicates Trays. Note 2 Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. 2002 Fairchild Semiconductor Corporation DS500169 GTLP18T612 Connection Diagrams Pin Assignments for SSOP and TSSOP Pin Assignments for FBGA Pin Descriptions Pin Names OEAB OEBA CEAB CEBA LEAB LEBA VREF CLKAB CLKBA A-to-B Output Enable Active LOW LVTTL Level B-to-A Output Enable Active LOW LVTTL Level A-to-B Clock/LE Enable Active LOW LVTTL Level B-to-A Clock/LE Enable Active LOW LVTTL Level A-to-B Latch Enable Transparent HIGH LVTTL Level B-to-A Latch Enable Transparent HIGH LVTTL Level GTLP Input Threshold Reference Voltage A-to-B Clock LVTTL Level B-to-A Clock LVTTL Level A-to-B Data Inputs or B-to-A 3-STATE Outputs B-to-A Data Inputs or A-to-B Open Drain Outputs FBGA Pin Assignments A1 OEAB CLKAB B2 A3 LEAB CEAB B4 A7 GND B8 A9 GND B10 A12 A11 GND B12 B11 A14 A13 VCC VREF B14 B13 A16 A15 OEBA CEBA B16 B15 A18 A17 LEBA CLKBA B18 B17 Top Thru View GTLP18T612 Functional Description The GTLP18T612 is an 18 bit registered transceiver containing D-type flip-flop, latch and transparent modes of operation for the data path. Data flow in each direction is controlled by the clock enables CEAB and CEBA , latch enables LEAB and LEBA , clock CLKAB and CLKBA and output enables OEAB and OEBA . The clock enables CEAB and CEBA and the output enables OEAB and OEBA control the 18 bits of data for the A-to-B and B-to-A directions respectively. For A-to-B data flow, when CEAB is LOW, the device operates on the LOW-to-HIGH transition of CLKAB for the flipflop and on the HIGH-to-LOW transition of LEAB for the latch path. That is, if CEAB is LOW and LEAB is LOW the A data is latched regardless as to the state of CLKAB HIGH or LOW and if LEAB is HIGH the device is in transparent mode. When OEAB is LOW the outputs are active. When OEAB is HIGH the outputs are HIGH impedance. The data flow of B-to-A is similar except that CEBA, OEBA, LEBA, and CLKBA are used. Logic Diagram Truth Table Note 3 Inputs Output Mode CEAB OEAB LEAB CLKAB A Latched

PDF Datasheet Preview

GTLP18T612 18-Bit LVTTL/GTLP Universal Bus Transceiver

GTLP18T612 18-Bit LVTTL/GTLP Universal Bus Transceiver

The GTLP18T612 is an 18-bit universal bus transceiver which provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed interface for cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP’s reduced output swing < 1V , reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic GTL JEDEC standard JESD8-3.

Fairchild’s GTLP has internal edge-rate control and is Process, Voltage, and Temperature PVT compensated. Its function is similar to BTL or GTL but with different output levels and receiver thresholds. GTLP output LOW level is less than 0.5V, the output HIGH is 1.5V and the receiver threshold is 1.0V.
s Bidirectional interface between GTLP and LVTTL logic levels
s Designed with edge rate control circuitry to reduce output noise on the GTLP port
s VREF pin provides external supply reference voltage for receiver threshold adjustibility
s Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature
s TTL compatible driver and control inputs s Designed using Fairchild advanced BiCMOS technology s Bushold data inputs on A port to eliminate the need for
external pull-up resistors for unused inputs s Power up/down and power off high impedance for live
insertion s Open drain on GTLP to support wired-or connection s Flow through pinout optimizes PCB layout s D-type flip-flop, latch and transparent data paths s A Port source/sink −24mA/+24mA s B Port sink +50mA s Also packaged in plastic Fine-Pitch Ball Grid Array

FBGA
Ordering Code:

Order Number Package Number

Package Description

GTLP18T612G Note 1 Note 2

BGA54A
54-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide

GTLP18T612MEA Note 2

MS56A
56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide

GTLP18T612MTD Note 2

MTD56
56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Note 1 Ordering code “G” indicates Trays.
Note 2 Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
2002 Fairchild Semiconductor Corporation DS500169

GTLP18T612

Connection Diagrams

Pin Assignments for SSOP and TSSOP

Pin Assignments for FBGA

Pin Descriptions

Pin Names

OEAB OEBA CEAB CEBA LEAB LEBA VREF CLKAB CLKBA

A-to-B Output Enable Active LOW LVTTL Level

B-to-A Output Enable Active LOW LVTTL Level

A-to-B Clock/LE Enable Active LOW LVTTL Level

B-to-A Clock/LE Enable Active LOW LVTTL Level

A-to-B Latch Enable Transparent HIGH LVTTL Level

B-to-A Latch Enable Transparent HIGH LVTTL Level

GTLP Input Threshold Reference Voltage

A-to-B Clock LVTTL Level

B-to-A Clock LVTTL Level

A-to-B Data Inputs or B-to-A 3-STATE Outputs

B-to-A Data Inputs or A-to-B Open Drain Outputs

FBGA Pin Assignments

A1 OEAB CLKAB B2

A3 LEAB CEAB B4

A7 GND B8

A9 GND B10

A12 A11 GND B12 B11

A14 A13 VCC VREF B14 B13

A16 A15 OEBA CEBA B16 B15

A18 A17 LEBA CLKBA B18 B17

Top Thru View

GTLP18T612

Functional Description

The GTLP18T612 is an 18 bit registered transceiver containing D-type flip-flop, latch and transparent modes of operation for the data path. Data flow in each direction is controlled by the clock enables CEAB and CEBA , latch enables LEAB and LEBA , clock CLKAB and CLKBA and output enables OEAB and OEBA . The clock enables CEAB and CEBA and the output enables OEAB and OEBA control the 18 bits of data for the A-to-B and B-to-A directions respectively. For A-to-B data flow, when CEAB is LOW, the device operates on the LOW-to-HIGH transition of CLKAB for the flipflop and on the HIGH-to-LOW transition of LEAB for the latch path. That is, if CEAB is LOW and LEAB is LOW the A data is latched regardless as to the state of CLKAB HIGH or LOW and if LEAB is HIGH the device is in transparent mode. When OEAB is LOW the outputs are active. When OEAB is HIGH the outputs are HIGH impedance. The data flow of B-to-A is similar except that CEBA, OEBA, LEBA, and CLKBA are used.

Logic Diagram

Truth Table

Note 3

Inputs

Output

Mode

CEAB OEAB LEAB CLKAB A

Latched

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Datasheet ID: GTLP18T612MTD 633858