8-Bit Programmable 2- to 3-Phase Synchronous Buck Controller ADP3193
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ADP3193JCPZ-RL (pdf) |
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8-Bit Programmable 2- to 3-Phase Synchronous Buck Controller ADP3193 Selectable 2- or 3-phase operation at up to 1 MHz per phase mV worst-case differential sensing error over temperature Logic-level PWM outputs for interface to external high power drivers Enhanced PWM flex mode for excellent load transient performance Active current balancing between all output phases Built-in power-good/crowbar blanking supports on-the-fly VID code changes Digitally programmable V to V output supports both VR10.x and VR11 specifications Programmable short-circuit protection with programmable latch-off delay Desktop PC power supplies for Next generation processors VRM modules The ADP31931 is a highly efficient, multiphase, synchronous buck switching regulator controller optimized for converting a 12 V main supply into the core supply voltage required by high performance Intel processors. It uses an internal 8-bit DAC to read a voltage identification VID code directly from the processor, which is used to set the output voltage between V and V. This device uses a multimode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VR size and efficiency. The phase relationship of the output signals can be programmed to provide 2- or 3-phase operation, allowing for the construction of up to three complementary buck switching stages. The ADP3193 also includes programmable no load offset and slope functions to adjust the output voltage as a function of the load current, optimally positioning it for a system transient. The ADP3193 also provides accurate and reliable short-circuit protection, adjustable current limiting, and a delayed powergood output that accommodates on-the-fly output voltage changes requested by the CPU. FUNCTIONAL BLOCK DIAGRAM GND 14 VCC 23 SHUNT REGULATOR UVLO SHUTDOWN 850mV + 150mV + CSREF + DAC 350mV PWRGD 2 DELAY ILIMIT 8 DELAY 7 RT RAMPADJ OSCILLATOR + CMP SET EN RESET 15 OD 22 PWM1 CURRENT BALANCING CIRCUIT + CMP + CMP 21 PWM2 RESET 2/3-PHASE 20 PWM3 DRIVER LOGIC RESET CROWBAR CURRENT LIMIT CURRENT MEASUREMENT Dynamic VID 12 Power-Good 12 Output Crowbar 12 Output Enable and UVLO 13 Application 19 Setting the Clock 19 Soft Start Delay 19 Current-Limit Latch-Off Delay Times 19 Inductor Selection 19 Current Sense 20 Inductor DCR Temperature Correction 21 Output Offset 21 COUT Selection 21 Power 22 Ramp Resistor 24 COMP Pin Ramp 24 Current-Limit 24 Feedback Loop Compensation 24 CIN Selection and Input Current di/dt Reduction.................. 26 Shunt Resistor 26 Tuning the ADP3193 27 Layout and Component Placement 29 Outline Dimensions 30 Ordering Guide 30 ADP3193 SPECIFICATIONS VCC = 5 V, FBRTN = GND, TA = 0°C to 85°C, unless otherwise noted.1 Table Parameter Symbol Conditions REFERENCE CURRENT Reference Bias Voltage VIREF Reference Bias Current IIREF RIREF = 100 kΩ ERROR AMPLIFIER Output Voltage Range2 Accuracy VCOMP VFB Relative to nominal DAC output, referenced to FBRTN see Figure 2 Differential Nonlinearity VFB BOOT In startup Input Bias Current FBRTN Current IFB IFBRTN IFB = IIREF Output Current ICOMP FB forced to VOUT 3% Gain Bandwidth Product GBW ERR COMP = FB Slew Rate COMP = FB BOOT Voltage Hold Time tBOOT CDELAY = 10 nF VID INPUTS Input Low Voltage Input High Voltage Input Current VID Transition Delay Time2 VIL VID VIH VID IIN VID VID X , VIDSEL VID X , VIDSEL VID code change to FB change No CPU Detection Turn-Off Delay Time2 VID code change to PWM going low OSCILLATOR Frequency Range2 ORDERING GUIDE Model Temperature Range ADP3193JCPZ-RL1 0°C to 85°C 1 Z = Pb-free part. Package Description 32-Lead Frame Chip Scale Package [LFCSP_VQ] Package Option Ordering Quantity CP-32-2 2,500 NOTES ADP3193 ADP3193 NOTES 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06263-0-8/06 A |
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