ADP3181JRQZ-RL

ADP3181JRQZ-RL Datasheet

ADP3181

Part	Datasheet
ADP3181JRQZ-RL	ADP3181JRQZ-RL (pdf)

Related Parts	Information
ADP3181JRUZ-REEL	ADP3181JRUZ-REEL

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5-Bit or 6-Bit Programmable 2-,3-,4-Phase Synchronous Buck Controller ADP3181 Selectable 2-, 3- or 4-phase operation at up to 1 MHz per phase mV worst-case mV differential sensing error over temperature Logic-level PWM outputs for interface to external high power drivers Active current balancing between all output phases Built-in power good/crowbar blanking supports on-the-fly VID code changes Digitally programmable output can be switched between VRM 9 5-bit and VRD 10 6-bit VID codes Programmable short-circuit protection with programmable latch-off delay Desktop PC power supplies for: Next-generation processors VRM modules The ADP3181 is a highly efficient multiphase synchronous buck-switching regulator controller optimized for converting a 12 V main supply into the core supply voltage required by high performance Intel processors. It uses an internal 6-bit DAC to read a voltage identification VID code directly from the processor, which is used to set the output voltage. The CPUID input selects whether the DAC codes match the VRM 9 or VRD 10 specifications. It uses a multimode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VR size and efficiency. The phase relationship of the output signals can be programmed to provide 2-, 3-, or 4-phase operation, allowing for the construction of up to four complementary buck-switching stages. The ADP3181 also includes programmable no-load offset and slope functions to adjust the output voltage as a function of the load current so that it is always optimally positioned for a system transient. The ADP3181 provides accurate and reliable short-circuit protection, adjustable current limiting, and a delayed power good output that accommodates on-the-fly output voltage changes requested by the CPU. The device is specified over the commercial temperature range of 0°C to +85°C and is available in a 28-lead TSSOP package. FUNCTIONAL BLOCK DIAGRAM VCC 28 EN 11 UVLO SHUTDOWN AND BIAS GND 19 DAC + 300mV CSREF DAC 250mV PWRGD 10 DELAY RAMPADJ RT OSCILLATOR CMP ADP3181 SET EN RESET 27 PWM1 CURRENTBALANCING CIRCUIT RESET 2-/3-/4-PHASE DRIVER LOGIC RESET 26 PWM2 25 PWM3 CMP RESET 24 PWM4 CROWBAR CURRENT LIMIT ILIMIT 15 EN Outline Dimensions 24 Ordering Guide 24 ADP3181 SPECIFICATIONS VCC = 12 V, FBRTN = GND, TA = 0°C to +85°C, unless otherwise noted.1 Table Parameter ERROR AMPLIFIER Output Voltage Range2 Accuracy Line Regulation Input Bias Current FBRTN Current Output Current Gain Bandwidth Product Slew Rate VID INPUTS Input Low Voltage Input High Voltage Input Current Pull-up Resistance Internal Pull-up Voltage VID Transition Delay Time2 No CPU Detection Turn-off Delay Time2 CPUID INPUT Low Voltage Input High Voltage VR 9 Detection Threshold Voltage Input Current Pull-up Resistance OSCILLATOR Frequency Range2 Frequency Variation Output Voltage RAMPADJ Output Voltage RAMPADJ Input Current Range CURRENT SENSE AMPLIFIER Offset Voltage Input Bias Current Gain Bandwidth Product Slew Rate Input Common-Mode Range Positioning Accuracy Output Voltage Range Output Current Symbol VCOMP VFB IFB IFBRTN IO ERR GBW ERR VIL VID VIH VID IVID RVID VIL CPUID VIH CPUID ICPUID RCPUID fOSC fPHASE VRT VRAMPADJ IRAMPADJ VOS CSA IBIAS CSSUM GBW CSA ICSCOMP Conditions Relative to nominal DAC output, referenced to FBRTN, CSSUM = CSCOMP. See Figure VCC = 10 V to 14 V FB forced to VOUT 3% COMP = FB CCOMP = 10 pF CPUID > V CPUID < V CPUID > V CPUID < V VID x = 0 V, CPUID > V VID x = 0 V, CPUID < V CPUID > V CPUID < V VID code change to FB change VID code change to PWM going low CPUID = 0 V TA = 25°C, RT = 250 4-phase TA = 25°C, RT = 115 4-phase TA = 25°C, RT = 75 4-phase RT = 100 to GND RAMPADJ FB CSSUM CSREF. See Figure CCSCOMP = 10 pF CSSUM and CSREF See Figure Min Typ Max Unit 14 17 µA 100 140 µA V/µs 40 70 µA 20 35 µA 40 60 20 µA 155 200 245 kHz −50 +50 mV 100 µA −3 +3 mV −50 ORDERING GUIDE Model ADP3181JRUZ-REEL1 1 Z = PB-free part. Temperature Range 0°C to +85°C Package Description Thin Shrink Reel Package Option RU-28 Quantity per Reel 2500 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04796-0-5/04 0

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5-Bit or 6-Bit Programmable 2-,3-,4-Phase Synchronous Buck Controller

ADP3181

Selectable 2-, 3- or 4-phase operation at up to 1 MHz per phase
mV worst-case mV differential sensing error over temperature

Logic-level PWM outputs for interface to external high power drivers

Active current balancing between all output phases Built-in power good/crowbar blanking supports on-the-fly

VID code changes Digitally programmable output can be switched between

VRM 9 5-bit and VRD 10 6-bit VID codes Programmable short-circuit protection with programmable
latch-off delay

Desktop PC power supplies for:

Next-generation processors

VRM modules

The ADP3181 is a highly efficient multiphase synchronous buck-switching regulator controller optimized for converting a 12 V main supply into the core supply voltage required by high performance Intel processors. It uses an internal 6-bit DAC to read a voltage identification VID code directly from the processor, which is used to set the output voltage. The CPUID input selects whether the DAC codes match the VRM 9 or VRD 10 specifications. It uses a multimode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VR size and efficiency. The phase relationship of the output signals can be programmed to provide 2-, 3-, or 4-phase operation, allowing for the construction of up to four complementary buck-switching stages.

The ADP3181 also includes programmable no-load offset and slope functions to adjust the output voltage as a function of the load current so that it is always optimally positioned for a system transient. The ADP3181 provides accurate and reliable short-circuit protection, adjustable current limiting, and a delayed power good output that accommodates on-the-fly output voltage changes requested by the CPU.

The device is specified over the commercial temperature range of 0°C to +85°C and is available in a 28-lead TSSOP package.

FUNCTIONAL BLOCK DIAGRAM

VCC 28

EN 11

UVLO SHUTDOWN

AND BIAS

GND 19

DAC + 300mV

CSREF

DAC 250mV

PWRGD 10

DELAY

RAMPADJ RT

OSCILLATOR CMP

ADP3181

SET EN RESET
27 PWM1

CURRENTBALANCING

CIRCUIT

RESET 2-/3-/4-PHASE DRIVER LOGIC

RESET
26 PWM2 25 PWM3

CMP RESET
24 PWM4

CROWBAR

CURRENT LIMIT

ILIMIT 15 EN
Outline Dimensions 24 Ordering Guide 24

ADP3181

SPECIFICATIONS

VCC = 12 V, FBRTN = GND, TA = 0°C to +85°C, unless otherwise noted.1 Table

Parameter ERROR AMPLIFIER Output Voltage Range2 Accuracy

Line Regulation Input Bias Current FBRTN Current Output Current Gain Bandwidth Product Slew Rate VID INPUTS Input Low Voltage

Input High Voltage

Input Current

Pull-up Resistance Internal Pull-up Voltage

VID Transition Delay Time2 No CPU Detection Turn-off Delay Time2 CPUID INPUT Low Voltage Input High Voltage VR 9 Detection Threshold Voltage Input Current Pull-up Resistance OSCILLATOR Frequency Range2 Frequency Variation

Output Voltage RAMPADJ Output Voltage RAMPADJ Input Current Range CURRENT SENSE AMPLIFIER Offset Voltage Input Bias Current Gain Bandwidth Product Slew Rate Input Common-Mode Range Positioning Accuracy Output Voltage Range Output Current

Symbol VCOMP VFB IFB IFBRTN IO ERR GBW ERR

VIL VID VIH VID IVID

RVID

VIL CPUID VIH CPUID ICPUID RCPUID fOSC fPHASE

VRT VRAMPADJ IRAMPADJ VOS CSA IBIAS CSSUM GBW CSA

ICSCOMP

Conditions

Relative to nominal DAC output, referenced to FBRTN, CSSUM = CSCOMP. See Figure VCC = 10 V to 14 V

FB forced to VOUT 3% COMP = FB CCOMP = 10 pF

CPUID > V CPUID < V CPUID > V CPUID < V VID x = 0 V, CPUID > V VID x = 0 V, CPUID < V

CPUID > V CPUID < V VID code change to FB change VID code change to PWM going low

CPUID = 0 V

TA = 25°C, RT = 250 4-phase TA = 25°C, RT = 115 4-phase TA = 25°C, RT = 75 4-phase RT = 100 to GND RAMPADJ FB

CSSUM CSREF. See Figure

CCSCOMP = 10 pF CSSUM and CSREF See Figure

Min Typ Max Unit
14 17 µA
100 140 µA

V/µs
40 70 µA
20 35 µA
40 60
20 µA
155 200 245 kHz
−50
+50 mV
100 µA
−3
+3 mV
−50
ORDERING GUIDE

Model ADP3181JRUZ-REEL1
1 Z = PB-free part.

Temperature Range 0°C to +85°C

Package Description Thin Shrink Reel

Package Option RU-28

Quantity per Reel 2500
2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.

D04796-0-5/04 0

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Datasheet ID: ADP3181JRQZ-RL 517853