FSTUD16211MTDX

FSTUD16211MTDX Datasheet

FSTUD16211 24-Bit Bus Switch with −2V Undershoot Protection and Level Shifting

Part	Datasheet
FSTUD16211MTDX	FSTUD16211MTDX (pdf)

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FSTUD16211 24-Bit Bus Switch with −2V Undershoot Protection and Level Shifting FSTUD16211 24-Bit Bus Switch with −2V Undershoot Protection and Level Shifting The Fairchild Switch FSTUD16211 provides 24-bits of high-speed CMOS TTL-compatible bus switching. The low on resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise. A diode to VCC has been integrated into the circuit to allow for level shifting between 5V inputs and 3.3V outputs. The device is organized as a 12-bit or 24-bit bus switch. When OE1 is LOW, the switch is ON and Port 1A is connected to Port 1B. When OE2 is LOW, Port 2A is connected to Port 2B. When OE1/2 is HIGH, a high impedance state exists between the A and B Ports. The A and B Ports have “undershoot hardened” circuit protection to support an extended range to 2.0V below ground. Fairchild’s integrated Undershoot Hardened Circuit senses undershoot at the I/O’s, and responds by preventing voltage differentials from developing and turning on the switch. s Undershoot hardened to −2V A and B Ports s Voltage level shifting s switch connection between two ports s Minimal propagation delay through the switch s Low lCC s Zero bounce in flow-through mode s Control inputs compatible with TTL level s See Applications Note AN-5008 for details s Also packaged in plastic Fine-Pitch Ball Grid Array FBGA Preliminary Ordering Code: Order Number Package Number Package Description FSTUD16211GX Note 1 BGA54A Preliminary 54-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide [TAPE and REEL] FSTUD16211MTD MTD56 56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Note 1 BGA package available in Tape and Reel only. Logic Diagram is a registered trademark of Fairchild Semiconductor Corporation. 2001 Fairchild Semiconductor Corporation DS500390 FSTUD16211 Connection Diagrams Pin Assignment for TSSOP Pin Assignment for FBGA Pin Descriptions Pin Name OE1, OE2 1A, 2A 1B, 2B NC Bus Switch Enables Bus A Bus B No Connect Pin Assignment for FBGA 1A2 1A1 NC OE2 1B1 1B2 1A4 1A3 1A7 OE1 1B3 1B4 1A6 1A5 GND 1B7 1B5 1B6 1A10 1A9 1A8 1B8 1B9 1B10 1A12 1A11 2A1 2B1 1B11 1B12 2A4 2A3 2A2 2B2 2B3 2B4 2A6 2A5 VCC GND 2B5 2B6 2A8 2A7 2A9 2B9 2B7 2B8 2A12 2A11 2A10 2B10 2B11 2B12 Truth Table Inputs Inputs/Outputs 1A, 1B 1A = 1B 1A = 1B 2A, 2B 2A = 2B Z 2A = 2B Top Thru View FSTUD16211 Absolute Maximum Ratings Note 2 Supply Voltage VCC −0.5V to +7.0V DC Switch Voltage VS Note 3 −2.0V to +7.0V DC Input Control Pin Voltage VIN Note 4 −0.5V to +7.0V DC Input Diode Current lIK VIN < 0V −50 mA DC Output IOUT 128 mA

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FSTUD16211 24-Bit Bus Switch with −2V Undershoot Protection and Level Shifting

FSTUD16211
24-Bit Bus Switch with −2V Undershoot Protection and Level Shifting

The Fairchild Switch FSTUD16211 provides 24-bits of high-speed CMOS TTL-compatible bus switching. The low on resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise. A diode to VCC has been integrated into the circuit to allow for level shifting between 5V inputs and 3.3V outputs.

The device is organized as a 12-bit or 24-bit bus switch. When OE1 is LOW, the switch is ON and Port 1A is connected to Port 1B. When OE2 is LOW, Port 2A is connected to Port 2B. When OE1/2 is HIGH, a high impedance state exists between the A and B Ports. The A and B Ports have “undershoot hardened” circuit protection to support an extended range to 2.0V below ground. Fairchild’s integrated Undershoot Hardened Circuit senses undershoot at the I/O’s, and responds by preventing voltage differentials from developing and turning on the switch.
s Undershoot hardened to −2V A and B Ports s Voltage level shifting s switch connection between two ports s Minimal propagation delay through the switch s Low lCC s Zero bounce in flow-through mode s Control inputs compatible with TTL level s See Applications Note AN-5008 for details s Also packaged in plastic Fine-Pitch Ball Grid Array

FBGA Preliminary
Ordering Code:

Order Number Package Number

Package Description

FSTUD16211GX Note 1

BGA54A Preliminary
54-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide [TAPE and REEL]

FSTUD16211MTD

MTD56
56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Note 1 BGA package available in Tape and Reel only.

Logic Diagram
is a registered trademark of Fairchild Semiconductor Corporation.
2001 Fairchild Semiconductor Corporation DS500390

FSTUD16211

Connection Diagrams

Pin Assignment for TSSOP

Pin Assignment for FBGA

Pin Descriptions

Pin Name

OE1, OE2 1A, 2A 1B, 2B NC

Bus Switch Enables Bus A Bus B

No Connect

Pin Assignment for FBGA
1A2 1A1 NC OE2 1B1 1B2
1A4 1A3 1A7 OE1 1B3 1B4
1A6 1A5 GND 1B7 1B5 1B6
1A10 1A9 1A8 1B8 1B9 1B10
1A12 1A11 2A1 2B1 1B11 1B12
2A4 2A3 2A2 2B2 2B3 2B4
2A6 2A5 VCC GND 2B5 2B6
2A8 2A7 2A9 2B9 2B7 2B8
2A12 2A11 2A10 2B10 2B11 2B12

Truth Table

Inputs

Inputs/Outputs
1A, 1B 1A = 1B 1A = 1B
2A, 2B 2A = 2B

Z 2A = 2B

Top Thru View

FSTUD16211

Absolute Maximum Ratings Note 2

Supply Voltage VCC
−0.5V to +7.0V

DC Switch Voltage VS Note 3
−2.0V to +7.0V

DC Input Control Pin Voltage VIN Note 4 −0.5V to +7.0V

DC Input Diode Current lIK VIN < 0V
−50 mA

DC Output IOUT
128 mA

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Datasheet ID: FSTUD16211MTDX 515561