FQD1P50TM

FQD1P50TM Datasheet

FQD1P50 / FQU1P50

Part	Datasheet
FQD1P50TM	FQD1P50TM (pdf)

Related Parts	Information
FQD1P50TF	FQD1P50TF

PDF Datasheet Preview
FQD1P50 / FQU1P50 FQD1P50 / FQU1P50 500V P-Channel MOSFET January 2009 These P-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for electronic lamp ballast based on complimentary half bridge. D-PAK G S FQD Series • -1.2A, -500V, RDS on = = -10 V • Low gate charge typical 11 nC • Low Crss typical pF • Fast switching • 100% avalanche tested • Improved dv/dt capability • RoHS Compliant I-PAK FQU Series ● ● Absolute Maximum Ratings TC = 25°C unless otherwise noted Symbol VDSS ID IDM VGSS EAS IAR EAR dv/dt PD TJ, TSTG TL Parameter Drain-Source Voltage Drain Current - Continuous TC = 25°C - Continuous TC = 100°C Drain Current - Pulsed Note 1 Gate-Source Voltage Single Pulsed Avalanche Energy Note 2 Avalanche Current Note 1 Repetitive Avalanche Energy Note 1 Peak Diode Recovery dv/dt Note 3 Power Dissipation TA = 25°C * Power Dissipation TC = 25°C - Derate above 25°C Operating and Storage Temperature Range Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds Thermal Characteristics Parameter Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Ambient * Thermal Resistance, Junction-to-Ambient

PDF Datasheet Preview

FQD1P50 / FQU1P50

FQD1P50 / FQU1P50
500V P-Channel MOSFET

January 2009

These P-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for electronic lamp ballast based on complimentary half bridge.

D-PAK

G S FQD Series
• -1.2A, -500V, RDS on = = -10 V
• Low gate charge typical 11 nC
• Low Crss typical pF
• Fast switching
• 100% avalanche tested
• Improved dv/dt capability
• RoHS Compliant

I-PAK

FQU Series
● ●

Absolute Maximum Ratings TC = 25°C unless otherwise noted

Symbol VDSS ID

IDM VGSS EAS IAR EAR dv/dt PD

TJ, TSTG TL

Parameter

Drain-Source Voltage

Drain Current
- Continuous TC = 25°C - Continuous TC = 100°C

Drain Current - Pulsed

Note 1

Gate-Source Voltage

Single Pulsed Avalanche Energy

Note 2

Avalanche Current

Note 1

Repetitive Avalanche Energy

Note 1

Peak Diode Recovery dv/dt

Note 3

Power Dissipation TA = 25°C * Power Dissipation TC = 25°C
- Derate above 25°C

Operating and Storage Temperature Range

Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds

Thermal Characteristics

Parameter

Thermal Resistance, Junction-to-Case

Thermal Resistance, Junction-to-Ambient *

Thermal Resistance, Junction-to-Ambient

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived FQD1P50TM Datasheet file may be downloaded here without warranties.

Datasheet ID: FQD1P50TM 515231