FIN3384MTDX

FIN3384MTDX Datasheet

FIN3385/FIN3383/FIN3384/FIN3386 Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer

Part	Datasheet
FIN3384MTDX	FIN3384MTDX (pdf)

Related Parts	Information
FIN3383MTDX	FIN3383MTDX

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FIN3385/FIN3383/FIN3384/FIN3386 Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer July 2009 FIN3385 / FIN3383 / FIN3384 / FIN3386 Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer Low Power Consumption 20MHz to 85MHz Shift Clock Support ±1V Common-Mode Range around 1.2V Narrow Bus Reduces Cable Size and Cost High Throughput up to 2.38Gbps Internal PLL with No External Component Compatible with TIA/EIA-644 Specification 56-Lead TSSOP Package The FIN3385 and FIN3383 transform 28-bit wide parallel LVTTL Low-Voltage TTL data into four serial LVDS Low Voltage Differential Signaling data streams. A phase-locked transmit clock is transmitted in parallel with the data stream over a separate LVDS link. Every cycle of transmit clock, 28 bits of input LVTTL data are sampled and transmitted. The FIN3386 and FIN3384 receive and convert the 4/3 serial LVDS data streams back into 28/21 bits of LVTTL data. Refer to Table 1 for a matrix summary of the serializers and deserializers available. For the FIN3385, at a transmit clock frequency of 85MHz, 28-bits of LVTTL data are transmitted at a rate of 595Mbps per LVDS channel. These chipsets solve EMI and cable size problems associated with wide and high-speed TTL interfaces. Ordering Information Operating Part Number Temperature Range FIN3383MTDX FIN3384MTDX -10 to +70°C FIN3385MTDX FIN3386MTDX Eco Status Package 56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153,6.1mm Wide Packing Method Tape and Reel For Fairchild’s definition of Eco Status, please visit: Table Display Panel Link Serializer / Deserializer Chip Matrix Part FIN3385 FIN3383 FIN3386 FIN3384 CLK Frequency 85 66 85 66 LVTTL In LVDS Out LVDS In LVTTL Out Package 56 TSSOP FIN3385/FIN3383/FIN3384/FIN3386 Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer Block Diagrams Figure FIN3385 and FIN3383 Transmitter Functional Diagram Figure FIN3386 and FIN3384 Receiver Functional Diagram 2003 Fairchild Semiconductor Corporation FIN3385/FIN3383/FIN3384/FIN3386 Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer Transmitters Pin Configuration Truth Table Inputs Outputs TxIn TxCLKIn /PwrDn 1 TxOut± TxCLKOut± Active Active HIGH LOW/ HIGH LOW/ HIGH Active LOW/ HIGH/ High Impedance HIGH LOW/ HIGH Don’t Care 2

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FIN3385/FIN3383/FIN3384/FIN3386 Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer

July 2009

FIN3385 / FIN3383 / FIN3384 / FIN3386 Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer

Low Power Consumption 20MHz to 85MHz Shift Clock Support ±1V Common-Mode Range around 1.2V Narrow Bus Reduces Cable Size and Cost High Throughput up to 2.38Gbps Internal PLL with No External Component Compatible with TIA/EIA-644 Specification 56-Lead TSSOP Package

The FIN3385 and FIN3383 transform 28-bit wide parallel LVTTL Low-Voltage TTL data into four serial LVDS Low Voltage Differential Signaling data streams. A phase-locked transmit clock is transmitted in parallel with the data stream over a separate LVDS link. Every cycle of transmit clock, 28 bits of input LVTTL data are sampled and transmitted.

The FIN3386 and FIN3384 receive and convert the 4/3 serial LVDS data streams back into 28/21 bits of LVTTL data. Refer to Table 1 for a matrix summary of the serializers and deserializers available. For the FIN3385, at a transmit clock frequency of 85MHz, 28-bits of LVTTL data are transmitted at a rate of 595Mbps per LVDS channel. These chipsets solve EMI and cable size problems associated with wide and high-speed TTL interfaces.
Ordering Information

Operating Part Number Temperature

Range

FIN3383MTDX FIN3384MTDX
-10 to +70°C FIN3385MTDX FIN3386MTDX

Eco Status

Package
56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153,6.1mm Wide

Packing Method Tape and Reel

For Fairchild’s definition of Eco Status, please visit:

Table Display Panel Link Serializer / Deserializer Chip Matrix

Part

FIN3385 FIN3383 FIN3386 FIN3384

CLK Frequency
85 66 85 66

LVTTL In

LVDS Out

LVDS In LVTTL Out Package
56 TSSOP

FIN3385/FIN3383/FIN3384/FIN3386 Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer

Block Diagrams

Figure FIN3385 and FIN3383 Transmitter Functional Diagram

Figure FIN3386 and FIN3384 Receiver Functional Diagram
2003 Fairchild Semiconductor Corporation

FIN3385/FIN3383/FIN3384/FIN3386 Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer

Transmitters Pin Configuration

Truth Table

Inputs

Outputs

TxIn

TxCLKIn /PwrDn 1 TxOut± TxCLKOut±

Active

Active

HIGH

LOW/ HIGH

LOW/ HIGH

Active

LOW/ HIGH/ High Impedance

HIGH

LOW/ HIGH

Don’t Care 2

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Datasheet ID: FIN3384MTDX 514685