FIN212ACGFX

FIN212ACGFX Datasheet

µSerDes FIN212AC 12-Bit Serializer / Deserializer Supporting Cameras and Small Displays Supporting Camera and small Displays

Part	Datasheet
FIN212ACGFX	FIN212ACGFX (pdf)

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µSerDes FIN212AC 12-Bit Serializer / Deserializer Supporting Cameras and Small Displays Supporting Camera and small Displays 12-Bit Serializer 12-Bit Deserializer March 2013 FIN212AC 12-Bit Serializer / Deserializer Supporting Cameras and Small Displays Data & Control Bits Frequency Capability Interface µController Usage Selectable Edge Rates Standby Current Core Voltage VDDA/S I/O Voltage VDDP ESD I/O to GND Package Ordering Information 12-Bit 40MHz Camera or LCD Microcontroller, RGB, YUV m68 & i86 Yes <10 µA to 3.6V to 3.6V 14kV 32-Terminal MLP 42-Ball USS-BGA FIN212ACMLX FIN212ACGFX The FIN212AC µSerDes is a low-power serializer / deserializer optimized for use in cell phone displays and camera paths. The device reduces a 12-bit data path to four wires. For camera applications, an additional master clock can be passed in the opposite direction of data flow. The device utilizes Fairchild’s proprietary ultra-low power, lowEMI technology. • Slider, Folder, & Clamshell Mobile Handsets • Printers • Security Cameras Related Resources • For samples and questions, please contact: Baseband FIN212AC Internal Termination Built-in voltage translation FIN212AC Camera Module Isolates interface for signal integrity Up to 40MHz Camera Module Figure Mobile Phone Example µSerDes FIN212AC 12-Bit Serializer / Deserializer Supporting Cameras and Small Displays FIN212AC Serializer DIRI=1 Pin Descriptions Pin Name DIRI CTL_ADJ Control to determine serializer or deserializer configuration. Adjusts CTL drive to compensate for environmental conditions and length. 0 Deserializer 1 Serializer 0 Low drive low power 1 High drive high power Configure frequency range for the PLL. See Table 1 Serializer DIRI=1 Control Pin. Configure frequency range for the PLL. See Table 1 Serializer DIRI=1 Control Pin. PLL0 Divide or adjust the serial frequency. See Table 1 Serializer DIRI=1 Control Pin. PLL1 CKREF STROBE DP[1:12] CKSO+ CKSODSO+ DSOCKSI+ CKSICKP /DIRO VDDP VDDS VDDA GND N/C Divide or adjust the serial frequency. See Table 1 Serializer DIRI=1 Control Pin. LV-CMOS clock input and PLL reference. LV-CMOS strobe input for latching data DP [1:12] into the serializer on the rising edge.

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µSerDes FIN212AC 12-Bit Serializer / Deserializer Supporting Cameras and Small Displays Supporting Camera and small Displays
12-Bit Serializer
12-Bit Deserializer

March 2013

FIN212AC 12-Bit Serializer / Deserializer Supporting Cameras and Small Displays

Data & Control Bits Frequency Capability Interface µController Usage Selectable Edge Rates Standby Current Core Voltage VDDA/S I/O Voltage VDDP ESD I/O to GND

Package
Ordering Information
12-Bit 40MHz Camera or LCD Microcontroller, RGB, YUV m68 & i86

Yes <10 µA to 3.6V to 3.6V
14kV 32-Terminal MLP 42-Ball USS-BGA

FIN212ACMLX FIN212ACGFX

The FIN212AC µSerDes is a low-power serializer / deserializer optimized for use in cell phone displays and camera paths. The device reduces a 12-bit data path to four wires. For camera applications, an additional master clock can be passed in the opposite direction of data flow. The device utilizes Fairchild’s proprietary ultra-low power, lowEMI technology.
• Slider, Folder, & Clamshell Mobile Handsets
• Printers
• Security Cameras

Related Resources
• For samples and questions, please contact:

Baseband

FIN212AC

Internal Termination

Built-in voltage translation

FIN212AC

Camera Module

Isolates interface for signal integrity

Up to 40MHz

Camera Module

Figure Mobile Phone Example
µSerDes FIN212AC 12-Bit Serializer / Deserializer Supporting Cameras and Small Displays

FIN212AC Serializer DIRI=1 Pin Descriptions

Pin Name DIRI

CTL_ADJ

Control to determine serializer or deserializer configuration.

Adjusts CTL drive to compensate for environmental conditions and length.
0 Deserializer 1 Serializer 0 Low drive low power 1 High drive high power

Configure frequency range for the PLL.

See Table 1 Serializer DIRI=1 Control Pin.

Configure frequency range for the PLL.

See Table 1 Serializer DIRI=1 Control Pin.

PLL0

Divide or adjust the serial frequency.

See Table 1 Serializer DIRI=1 Control Pin.

PLL1

CKREF STROBE DP[1:12] CKSO+ CKSODSO+ DSOCKSI+ CKSICKP
/DIRO

VDDP VDDS VDDA GND N/C

Divide or adjust the serial frequency.

See Table 1 Serializer DIRI=1 Control Pin.

LV-CMOS clock input and PLL reference.

LV-CMOS strobe input for latching data DP [1:12] into the serializer on the rising edge.

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Datasheet ID: FIN212ACGFX 514681