FIN1026MTC

FIN1026MTC Datasheet

FIN1026 3.3V LVDS 2-Bit High Speed Differential Receiver

Part	Datasheet
FIN1026MTC	FIN1026MTC (pdf)

Related Parts	Information
FIN1026MTCX	FIN1026MTCX

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FIN1026 3.3V LVDS 2-Bit High Speed Differential Receiver FIN1026 3.3V LVDS 2-Bit High Speed Differential Receiver This dual receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling LVDS technology. The receiver translates LVDS levels, with a typical differential input threshold of 100mV, to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transfer of clock and data. The FIN1026 can be paired with its companion driver, the FIN1025, or any other LVDS driver. s Greater than 400Mbs data rate s Flow-through pinout simplifies PCB layout s 3.3V power supply operation s 0.4ns maximum differential pulse skew s 2.5ns maximum propagation delay s Low power dissipation s Power-Off protection s Fail safe protection for open-circuit, shorted and termi- nated non-driven input conditions s Meets or exceeds the TIA/EIA-644 LVDS standard s 14-Lead TSSOP package saves space Ordering Code: Order Number Package Number Package Description FIN1026MTC MTC14 14-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Name ROUT1, ROUT2 RIN1+, RIN2+ RIN1−, RIN2− EN VCC GND NC Description LVTTL Data Outputs Non-Inverting LVDS Inputs Inverting LVDS Inputs Driver Enable Pin Inverting Driver Enable Pin Power Supply Ground No Connect Truth Table Inputs Outputs RIN+ RIN− L or Open H L or Open L L or Open Fail Safe Condition L or Open H = HIGH Logic Level L = LOW Logic Level X = Don’t Care Z = High Impedance Fail Safe = Open, Shorted, Terminated ROUT H L H Z 2002 Fairchild Semiconductor Corporation DS500784 FIN1026 Absolute Maximum Ratings Note 1 Supply Voltage VCC LVDS DC Input Voltage VIN LVTTL DC Input Voltage VIN DC Output Voltage VOUT DC Output Current IO Storage Temperature Range TSTG Max Junction Temperature TJ Lead Temperature TL Soldering, 10 seconds ESD Human Body Model ESD Machine Model −0.5V to +4.6V −0.5V to +4.6V −0.5V to 6V −0.5V to 6V 16mA −65°C to +150°C 150°C 260°C 10,000V 600V Recommended Operating Conditions Supply Voltage VCC Magnitude of Differential Voltage 3.0V to 3.6V \|VID\| 100mV to VCC Common-Mode Input Voltage VIC 0.05V to 2.35V Input Voltage VIN 0 to VCC Operating Temperature TA

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FIN1026 3.3V LVDS 2-Bit High Speed Differential Receiver

FIN1026 3.3V LVDS 2-Bit High Speed Differential Receiver

This dual receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling LVDS technology. The receiver translates LVDS levels, with a typical differential input threshold of 100mV, to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transfer of clock and data.

The FIN1026 can be paired with its companion driver, the FIN1025, or any other LVDS driver.
s Greater than 400Mbs data rate s Flow-through pinout simplifies PCB layout s 3.3V power supply operation s 0.4ns maximum differential pulse skew s 2.5ns maximum propagation delay s Low power dissipation s Power-Off protection s Fail safe protection for open-circuit, shorted and termi-
nated non-driven input conditions s Meets or exceeds the TIA/EIA-644 LVDS standard s 14-Lead TSSOP package saves space
Ordering Code:

Order Number Package Number

Package Description

FIN1026MTC

MTC14
14-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Name ROUT1, ROUT2 RIN1+, RIN2+ RIN1−, RIN2−

EN VCC GND NC

Description LVTTL Data Outputs Non-Inverting LVDS Inputs Inverting LVDS Inputs Driver Enable Pin

Inverting Driver Enable Pin Power Supply Ground No Connect

Truth Table

Inputs

Outputs

RIN+

RIN−

L or Open H

L or Open L

L or Open Fail Safe Condition

L or Open

H = HIGH Logic Level L = LOW Logic Level X = Don’t Care Z = High Impedance Fail Safe = Open, Shorted, Terminated

ROUT H L H Z
2002 Fairchild Semiconductor Corporation DS500784

FIN1026

Absolute Maximum Ratings Note 1

Supply Voltage VCC LVDS DC Input Voltage VIN LVTTL DC Input Voltage VIN DC Output Voltage VOUT DC Output Current IO Storage Temperature Range TSTG Max Junction Temperature TJ Lead Temperature TL

Soldering, 10 seconds

ESD Human Body Model

ESD Machine Model
−0.5V to +4.6V −0.5V to +4.6V
−0.5V to 6V −0.5V to 6V
16mA −65°C to +150°C
150°C
260°C 10,000V
600V

Recommended Operating Conditions

Supply Voltage VCC Magnitude of Differential Voltage
3.0V to 3.6V
|VID|
100mV to VCC

Common-Mode Input Voltage VIC
0.05V to 2.35V

Input Voltage VIN
0 to VCC

Operating Temperature TA

More datasheets: 1866 | G2G085-AB02-01 | G2G085-AB04-10 | 26030 | 6435 SL001 | 6435 SL002 | 571 | CDB4955A | 1740 | FIN1026MTCX

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Datasheet ID: FIN1026MTC 514665