FIN1022MTC

FIN1022MTC Datasheet

FIN1022 2 X 2 LVDS High Speed Crosspoint Switch

Part	Datasheet
FIN1022MTC	FIN1022MTC (pdf)

Related Parts	Information
FIN1022MTCX	FIN1022MTCX
FIN1022M	FIN1022M
FIN1022MX	FIN1022MX

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FIN1022 2 X 2 LVDS High Speed Crosspoint Switch FIN1022 2 X 2 LVDS High Speed Crosspoint Switch This non-blocking 2x2 crosspoint switch has a fully differential input to output data path for low noise generation and low pulse width distortion. The device can be used as a high speed crosspoint switch, 2:1 multiplexer, 1:2 demultiplexer or 1:2 signal splitter. The inputs can directly interface with LVDS and LVPECL levels. s Low jitter, 800 Mbps full differential data path s Worst case jitter of 190ps with PRBS = 223 − 1 data pattern at 800 Mbps s Rail-to-rail common mode range is 0.5V to 3.25V s Worst case power dissipation is less than 126 mW s Open-circuit fail safe protection s Fast switch time of ns typical s 35 ps typical pin channel to channel skew s 3.3V power supply operation s Non-blocking switch s LVDS receiver inputs accept LVPECL signals directly s kV HBM ESD protection s 16-lead SOIC package and TSSOP package s Inter-operates with TIA/EIA 644-1995 specification s See the Fairchild Interface Solutions web page for cross reference information: Ordering Code: Order Number Package Number Package Description FIN1022M M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow FIN1022MTC MTC16 16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol 2001 Fairchild Semiconductor Corporation DS500653 FIN1022 Connection Diagram Pin Descriptions Pin Name RIN0+, RIN1+ LVDS non-inverting data inputs RIN0−, RIN1− LVDS inverting data inputs DOUT0+, DOUT1+ LVDS non-inverting data outputs DOUT0−, DOUT1− LVDS inverting data outputs LVTTL input for enabling DOUT0+/DOUT0− LVTTL input for enabling DOUT1+/DOUT1− SEL0 LVTTL input for selecting RIN0+/RIN0− or RIN1+/RIN1− for output DOUT0+/DOUT0− SEL1 LVTTL input for selecting RIN0+/RIN0− or RIN1+/RIN1− for output DOUT1+/DOUT1− Power Supply Ground Function Table SEL0 L/O L/O H X L/O H X O = OPEN Inputs SEL1 EN0 L/O L/O L / O = LOW or OPEN Outputs DOUT0+ DOUT0− DOUT1+ DOUT1− Mode RIN0+ RIN0− RIN0+ RIN0− 1:2 Splitter RIN0+ RIN0− RIN1+ RIN1− Repeater RIN1+ RIN1− RIN0+ RIN0− Switch RIN1+ RIN1− RIN1+ RIN1− 1:2 Splitter RIN0+ RIN0− DOUT0 Disabled RIN1+ RIN1− DOUT0 Disabled L / O RIN0+ RIN0− L / O RIN1+ RIN1− H = HIGH Logic Level L = LOW Logic Level

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FIN1022 2 X 2 LVDS High Speed Crosspoint Switch

FIN1022 2 X 2 LVDS High Speed Crosspoint Switch

This non-blocking 2x2 crosspoint switch has a fully differential input to output data path for low noise generation and low pulse width distortion. The device can be used as a high speed crosspoint switch, 2:1 multiplexer, 1:2 demultiplexer or 1:2 signal splitter. The inputs can directly interface with LVDS and LVPECL levels.
s Low jitter, 800 Mbps full differential data path s Worst case jitter of 190ps
with PRBS = 223 − 1 data pattern at 800 Mbps s Rail-to-rail common mode range is 0.5V to 3.25V s Worst case power dissipation is less than 126 mW s Open-circuit fail safe protection s Fast switch time of ns typical s 35 ps typical pin channel to channel skew s 3.3V power supply operation s Non-blocking switch s LVDS receiver inputs accept LVPECL signals directly s kV HBM ESD protection s 16-lead SOIC package and TSSOP package s Inter-operates with TIA/EIA 644-1995 specification s See the Fairchild Interface Solutions web page for cross
reference information:
Ordering Code:

Order Number Package Number

Package Description

FIN1022M

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow

FIN1022MTC

MTC16
16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol
2001 Fairchild Semiconductor Corporation DS500653

FIN1022

Connection Diagram

Pin Descriptions

Pin Name

RIN0+, RIN1+

LVDS non-inverting data inputs

RIN0−, RIN1−

LVDS inverting data inputs

DOUT0+, DOUT1+ LVDS non-inverting data outputs

DOUT0−, DOUT1− LVDS inverting data outputs

LVTTL input for enabling DOUT0+/DOUT0−

LVTTL input for enabling DOUT1+/DOUT1−

SEL0

LVTTL input for selecting RIN0+/RIN0− or RIN1+/RIN1− for output DOUT0+/DOUT0−

SEL1

LVTTL input for selecting RIN0+/RIN0− or RIN1+/RIN1− for output DOUT1+/DOUT1−

Power Supply

Ground

Function Table

SEL0 L/O L/O

H X L/O H X

O = OPEN

Inputs

SEL1 EN0

L/O L/O

L / O = LOW or OPEN

Outputs DOUT0+ DOUT0− DOUT1+ DOUT1−

Mode

RIN0+ RIN0− RIN0+ RIN0− 1:2 Splitter

RIN0+ RIN0− RIN1+ RIN1− Repeater

RIN1+ RIN1− RIN0+ RIN0− Switch

RIN1+ RIN1− RIN1+ RIN1− 1:2 Splitter

RIN0+ RIN0− DOUT0 Disabled

RIN1+ RIN1− DOUT0 Disabled

L / O RIN0+ RIN0−

L / O RIN1+ RIN1−

H = HIGH Logic Level

L = LOW Logic Level

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Datasheet ID: FIN1022MTC 514663