DM96S02N

DM96S02N Datasheet

DM96S02 Dual Retriggerable Resettable Monostable Multivibrator

Part	Datasheet
DM96S02N	DM96S02N (pdf)

PDF Datasheet Preview
DM96S02 Dual Retriggerable Resettable Monostable Multivibrator DM96S02 Dual Retriggerable Resettable Monostable Multivibrator The DM96S02 is a dual retriggerable and resettable monostable multivibrator. This one-shot provides exceptionally wide delay range, pulse width stability, predictable accuracy and immunity to noise. The pulse width is set by an external resistor and capacitor. Resistor values up to for the DM96S02 reduce required capacitor values. Hysteresis is provided on the positive trigger input of the DM96S02 for increased noise immunity. Order Code: Order Number Package Number Package Description DM96S02M M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow DM96S02N N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Diagram Connection Diagram VCC = Pin 16 GND = Pin 8 Pin Descriptions Pin Names Trigger Input Active Falling Edge Schmitt Trigger Input Active Rising-Edge CD Q1 - 2 Direct Clear Input Active-LOW True Pulse Output Q1 - 2 Complementary Pulse Output CX1, 2 RX1,2 External Capacitor Connection External Resistor Connection Triggering Truth Table Pin Number H = HIGH Voltage Level VIH L = LOW Voltage Level VIL X = Immaterial either H or L H L = HIGH-to-LOW Voltage Level transition L H = LOW-to-HIGH Voltage Level transition Operation Trigger Reset 1999 Fairchild Semiconductor Corporation DS009810.prf DM96S02 Functional Description The 96S02 dual retriggerable resettable monostable multivibrator has tow DC coupled trigger inputs per function, one active LOW I0 and one active HIGH I1 . The I1 input utilizes an internal Schmitt trigger with hysteresis of 0.3V to provide increased noise immunity. The use of active HIGH and LOW inputs allows wither rising or falling edge triggering and optional non-retriggerable operation. The inputs are DC coupled making triggering independent of input transition times. When input conditions for triggering are met the Q output goes HIGH and the external capacitor is rapidly discharged and then allowed to recharge. An input Block Diagram trigger which occurs during the timing cycle will retrigger the circuit and result in Q remaining HIGH. The output pulse may be terminated Q to the LOW state at any time by setting the Direct Clear input LOW. Retriggering may be inhibited by tying the Q output to I0 or the Q output to I1. Differential sensing techniques are used to obtain excellent stability over temperature and power supply variations and a feedback Darlington capacitor discharge circuit minimizes pulse width variation from unit to unit. Schottky TTL output stages provide high switching speeds and output compatibility with all TTL logic families. DM96S02 Operation Notes TIMING An external resistor RX and an external capacitor CX are required as shown in the Logic Diagram. The value of RX may vary from to DM96S02 . The value of CX may vary from 0 to any necessary value available. If however, the capacitor has significant leakage relative to VCC/RX the timing equations may not represent the pulse width obtained. The output pulse width tW for RX 10 and CX 1000 pF is determined as follows: tW = RXCX Where RX is in CX is in pF, t is in ns or RTX is in CX is in µF, t is in ms. The output pulse width for RX < 10 or CX < 1000 pF should be determined from pulse width versus CX or RX graphs. To obtain variable pulse width by remote trimming, the following circuit is recommended: Under any operating condition, CX and RX Min must be kept as close to the circuit as possible to minimize stray capacitance and reduce noise pickup. VCC and ground wiring should conform to good high frequency standards so that switching transients on VCC and ground leads do not cause interaction between one shots. Use of a µF to 0.1µF bypass capacitor between VCC and ground located near the circuit is recommended. TRIGGERING The minimum negative pulse width into I0 is ns the minimum positive pulse width into I1 is 12 ns.

PDF Datasheet Preview

DM96S02 Dual Retriggerable Resettable Monostable Multivibrator

DM96S02 Dual Retriggerable Resettable Monostable Multivibrator

The DM96S02 is a dual retriggerable and resettable monostable multivibrator. This one-shot provides exceptionally wide delay range, pulse width stability, predictable accuracy and immunity to noise. The pulse width is set by
an external resistor and capacitor. Resistor values up to for the DM96S02 reduce required capacitor values. Hysteresis is provided on the positive trigger input of the DM96S02 for increased noise immunity.

Order Code:

Order Number Package Number

Package Description

DM96S02M

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow

DM96S02N

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Diagram

Connection Diagram

VCC = Pin 16

GND = Pin 8

Pin Descriptions

Pin Names

Trigger Input Active Falling Edge

Schmitt Trigger Input Active Rising-Edge

CD Q1 - 2

Direct Clear Input Active-LOW True Pulse Output

Q1 - 2

Complementary Pulse Output

CX1, 2 RX1,2

External Capacitor Connection External Resistor Connection

Triggering Truth Table

Pin Number

H = HIGH Voltage Level VIH L = LOW Voltage Level VIL X = Immaterial either H or L H L = HIGH-to-LOW Voltage Level transition

L H = LOW-to-HIGH Voltage Level transition

Operation

Trigger Reset
1999 Fairchild Semiconductor Corporation DS009810.prf

DM96S02

Functional Description

The 96S02 dual retriggerable resettable monostable multivibrator has tow DC coupled trigger inputs per function, one active LOW I0 and one active HIGH I1 . The I1 input utilizes an internal Schmitt trigger with hysteresis of 0.3V to provide increased noise immunity. The use of active HIGH and LOW inputs allows wither rising or falling edge triggering and optional non-retriggerable operation. The inputs are DC coupled making triggering independent of input transition times. When input conditions for triggering are met the Q output goes HIGH and the external capacitor is rapidly discharged and then allowed to recharge. An input

Block Diagram
trigger which occurs during the timing cycle will retrigger the circuit and result in Q remaining HIGH. The output pulse may be terminated Q to the LOW state at any time by setting the Direct Clear input LOW. Retriggering may be inhibited by tying the Q output to I0 or the Q output to I1. Differential sensing techniques are used to obtain excellent stability over temperature and power supply variations and a feedback Darlington capacitor discharge circuit minimizes pulse width variation from unit to unit. Schottky TTL output stages provide high switching speeds and output compatibility with all TTL logic families.

DM96S02

Operation Notes

TIMING

An external resistor RX and an external capacitor CX are required as shown in the Logic Diagram. The value of RX may vary from to DM96S02 .

The value of CX may vary from 0 to any necessary value available. If however, the capacitor has significant leakage relative to VCC/RX the timing equations may not represent the pulse width obtained.

The output pulse width tW for RX 10 and CX 1000 pF is determined as follows:
tW = RXCX

Where RX is in CX is in pF, t is in ns or RTX is in CX is in µF, t is in ms.

The output pulse width for RX < 10 or CX < 1000 pF should be determined from pulse width versus CX or RX graphs.

To obtain variable pulse width by remote trimming, the following circuit is recommended:

Under any operating condition, CX and RX Min must be kept as close to the circuit as possible to minimize stray capacitance and reduce noise pickup.

VCC and ground wiring should conform to good high frequency standards so that switching transients on VCC and ground leads do not cause interaction between one shots. Use of a µF to 0.1µF bypass capacitor between VCC and ground located near the circuit is recommended.

TRIGGERING

The minimum negative pulse width into I0 is ns the minimum positive pulse width into I1 is 12 ns.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived DM96S02N Datasheet file may be downloaded here without warranties.

Datasheet ID: DM96S02N 513855