DM74S280N

DM74S280N Datasheet

DM74S280 9-Bit Parity Generator/Checker

Part	Datasheet
DM74S280N	DM74S280N (pdf)

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DM74S280 9-Bit Parity Generator/Checker DM74S280 9-Bit Parity Generator/Checker These universal, nine-bit parity generators/checkers utilize Schottky-clamped TTL high-performance circuitry, and feature odd/even outputs to facilitate operation of either odd or even parity applications. The word-length capability is easily expanded by cascading. The DM74S280 can be used to upgrade the performance of most systems utilizing the DM74180 parity generator/ checker. Although the DM74S280 is implemented without expander inputs, the corresponding function is provided by the availability of all input at pin 4, and no internal connection at pin This permits the DM74S280 to be substituted for the 180 in existing designs to produce an identical function, even if DM74S280’s are mixed with existing 180’s. Input buffers are provided so that each input represents only one normal 74S load, and full fan-out to 10 normal Series 74S loads is available from each of the outputs at low logic levels. A fan-out to 20 normal Series 74S loads is provided at high logic levels, to facilitate connection of unused inputs to used inputs. s Generates either odd or even parity for nine data lines s Cascadable for N-bits s Can be used to upgrade existing systems using MSI par- ity circuits s Typical data-to-output ns Ordering Code: Order Number Package Number Package Description DM74S280M M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, Narrow DM74S280N N14A 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Number of Inputs A Thru I that are HIGH 0, 2, 4, 6, 8 1, 3, 5, 7, 9 Outputs Even 2000 Fairchild Semiconductor Corporation DS006483 DM74S280 Logic Diagram Three DM74S280’s can be used to implement a 25-line parity generator/checker. This arrangement will provide parity in typically 25 ns. See Figure Longer word lengths can be implemented by cascading DM74S280’s. As shown in Figure 2, parity can be generated for word lengths up to 81 bits in typically 25 ns. FIGURE 25-Line Parity/Generator Checker FIGURE 81-Line Parity/Generator Checker DM74S280 Absolute Maximum Ratings Note 1 Supply Voltage Input Voltage 5.5V Operating Free Air Temperature Range 0°C to +70°C Storage Temperature Range −65°C to +150°C Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Recommended Operating Conditions VCC VIH VIL IOH IOL TA Parameter Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature Electrical Characteristics over recommended operating free air temperature range unless otherwise noted Parameter Conditions Nom 5 Input Clamp Voltage VCC = Min, II=−18 mA HIGH Level Output Voltage LOW Level Output Voltage VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL =Max VIH = Min, VIL = Max

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DM74S280 9-Bit Parity Generator/Checker

DM74S280 9-Bit Parity Generator/Checker

These universal, nine-bit parity generators/checkers utilize Schottky-clamped TTL high-performance circuitry, and feature odd/even outputs to facilitate operation of either odd or even parity applications. The word-length capability is easily expanded by cascading.

The DM74S280 can be used to upgrade the performance of most systems utilizing the DM74180 parity generator/ checker. Although the DM74S280 is implemented without expander inputs, the corresponding function is provided by the availability of all input at pin 4, and no internal connection at pin This permits the DM74S280 to be substituted for the 180 in existing designs to produce an identical function, even if DM74S280’s are mixed with existing 180’s.

Input buffers are provided so that each input represents only one normal 74S load, and full fan-out to 10 normal Series 74S loads is available from each of the outputs at low logic levels. A fan-out to 20 normal Series 74S loads is provided at high logic levels, to facilitate connection of unused inputs to used inputs.
s Generates either odd or even parity for nine data lines s Cascadable for N-bits s Can be used to upgrade existing systems using MSI par-
ity circuits s Typical data-to-output ns
Ordering Code:

Order Number Package Number

Package Description

DM74S280M

M14A
14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, Narrow

DM74S280N

N14A
14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

Number of Inputs A Thru I that are HIGH
0, 2, 4, 6, 8 1, 3, 5, 7, 9

Outputs

Even
2000 Fairchild Semiconductor Corporation DS006483

DM74S280

Logic Diagram

Three DM74S280’s can be used to implement a 25-line parity generator/checker. This arrangement will provide parity in typically 25 ns. See Figure

Longer word lengths can be implemented by cascading DM74S280’s. As shown in Figure 2, parity can be generated for word lengths up to 81 bits in typically 25 ns.

FIGURE 25-Line Parity/Generator Checker

FIGURE 81-Line Parity/Generator Checker

DM74S280

Absolute Maximum Ratings Note 1

Supply Voltage

Input Voltage
5.5V

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range
−65°C to +150°C

Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Recommended Operating Conditions

VCC VIH VIL IOH IOL TA

Parameter Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature

Electrical Characteristics
over recommended operating free air temperature range unless otherwise noted

Parameter

Conditions

Nom 5

Input Clamp Voltage

VCC = Min, II=−18 mA

HIGH Level

Output Voltage

LOW Level

Output Voltage

VCC = Min, IOH = Max

VIL = Max, VIH = Min

VCC = Min, IOL =Max

VIH = Min, VIL = Max

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Datasheet ID: DM74S280N 513841