DM74S112N

DM74S112N Datasheet

DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs

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DM74S112N	DM74S112N (pdf)

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DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the negative going edge of the clock pulse. Data on the J and K inputs can be changed while the clock is HIGH or LOW without affecting the outputs as long as setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs. Ordering Code: Order Number Package Number Package Description DM74S112 N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Connection Diagram Function Table Inputs Outputs PR CLR CLK J K Toggle H = HIGH Logic Level X = Either LOW or HIGH Logic Level L = LOW Logic Level = Negative going edge of pulse. Q0 = The output logic level of Q before the indicated input conditions were established. * = This configuration is nonstable that is, it will not persist when either the preset and/or clear inputs return to its inactive HIGH level. Toggle = Each output changes to the complement of its previous level on each falling edge of the clock pulse. 2000 Fairchild Semiconductor Corporation DS006459 DM74S112 Absolute Maximum Ratings Note 1 Supply Voltage Input Voltage 5.5V Operating Free Air Temperature Range 0°C to +70°C Storage Temperature Range −65°C to +150°C Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Recommended Operating Conditions Parameter Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current fCLK Clock Frequency Note 2 fCLK Clock Frequency Note 3 Pulse Width Clock HIGH Note 2 Clock LOW

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DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs

DM74S112

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs

This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the negative going edge of the clock pulse. Data on the J and K inputs can be changed while the clock is HIGH or LOW without affecting the outputs as long as setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.
Ordering Code:

Order Number Package Number

Package Description

DM74S112

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide

Connection Diagram

Function Table

Inputs

Outputs

PR CLR CLK J K

Toggle

H = HIGH Logic Level X = Either LOW or HIGH Logic Level L = LOW Logic Level = Negative going edge of pulse. Q0 = The output logic level of Q before the indicated input conditions were
established. * = This configuration is nonstable that is, it will not persist when either the
preset and/or clear inputs return to its inactive HIGH level.

Toggle = Each output changes to the complement of its previous level on each falling edge of the clock pulse.
2000 Fairchild Semiconductor Corporation DS006459

DM74S112

Absolute Maximum Ratings Note 1

Supply Voltage

Input Voltage
5.5V

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range
−65°C to +150°C

Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Recommended Operating Conditions

Parameter

Supply Voltage

HIGH Level Input Voltage

LOW Level Input Voltage

HIGH Level Output Current

LOW Level Output Current
fCLK

Clock Frequency Note 2
fCLK

Clock Frequency Note 3

Pulse Width

Clock HIGH

Note 2

Clock LOW

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Datasheet ID: DM74S112N 513825