DM74LS74AN

DM74LS74AN Datasheet

DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs

Part	Datasheet
DM74LS74AN	DM74LS74AN (pdf)

Related Parts	Information
DM74LS74AM	DM74LS74AM

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DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs This device contains two independent positive-edge-triggered D flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the D input may be changed while the clock is LOW or HIGH without affecting the outputs as long as the data setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs. Ordering Code: Order Number Package Number Package Description DM74LS74AM M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, Narrow DM74LS85ASJ M14D 14-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide DM74LS74AN N14A 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs Outputs PR CLR CLK D X H Note 1 H Note 1 H = HIGH Logic Level X = Either LOW or HIGH Logic Level L = LOW Logic Level = Positive-going Transition Q0 = The output logic level of Q before the indicated input conditions were established. Note 1 This configuration is nonstable that is, it will not persist when either the preset and/or clear inputs return to their inactive HIGH level. 2000 Fairchild Semiconductor Corporation DS006373 DM74LS74A Absolute Maximum Ratings Note 2 Supply Voltage Input Voltage Operating Free Air Temperature Range 0°C to +70°C Storage Temperature Range −65°C to +150°C Note 2 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Recommended Operating Conditions Parameter Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current fCLK Clock Frequency Note 3 fCLK Clock Frequency Note 4 Pulse Width Clock HIGH Note 3 Preset LOW Clear LOW Pulse Width Note 4 Clock HIGH Preset LOW Clear LOW Setup Time Note 3 Note 5 Setup Time Note 4 Note 5

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DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs

DM74LS74A

Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs

This device contains two independent positive-edge-triggered D flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the D input may be changed while the clock is LOW or HIGH without affecting the outputs as long as the data setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.
Ordering Code:

Order Number Package Number

Package Description

DM74LS74AM

M14A
14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, Narrow

DM74LS85ASJ

M14D
14-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide

DM74LS74AN

N14A
14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

Inputs

Outputs

PR CLR CLK D

X H Note 1 H Note 1

H = HIGH Logic Level X = Either LOW or HIGH Logic Level L = LOW Logic Level = Positive-going Transition Q0 = The output logic level of Q before the indicated input conditions were established.

Note 1 This configuration is nonstable that is, it will not persist when either the preset and/or clear inputs return to their inactive HIGH level.
2000 Fairchild Semiconductor Corporation DS006373

DM74LS74A

Absolute Maximum Ratings Note 2

Supply Voltage

Input Voltage

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range
−65°C to +150°C

Note 2 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Recommended Operating Conditions

Parameter

Supply Voltage

HIGH Level Input Voltage

LOW Level Input Voltage

HIGH Level Output Current

LOW Level Output Current
fCLK

Clock Frequency Note 3
fCLK

Clock Frequency Note 4

Pulse Width

Clock HIGH

Note 3

Preset LOW

Clear LOW

Pulse Width

Note 4

Clock HIGH

Preset LOW

Clear LOW

Setup Time Note 3 Note 5

Setup Time Note 4 Note 5

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Datasheet ID: DM74LS74AN 513811