DM74LS373WM

DM74LS373WM Datasheet

DM74LS373<br>• DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops

Part	Datasheet
DM74LS373WM	DM74LS373WM (pdf)

Related Parts	Information
DM74LS373N	DM74LS373N
DM74LS374N	DM74LS374N
DM74LS374WM	DM74LS374WM

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DM74LS373 • DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops DM74LS373 • DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops These 8-bit registers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the DM74LS373 are transparent Dtype latches meaning that while the enable G is HIGH the Q outputs will follow the data D inputs. When the enable is taken LOW the output will be latched at the level of the data that was set up. The eight flip-flops of the DM74LS374 are edge-triggered D-type flip flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D inputs. A buffered output control input can be used to place the eight outputs in either a normal logic state HIGH or LOW logic levels or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significantly. The output control does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered even while the outputs are OFF. s Choice of 8 latches or 8 D-type flip-flops in a single package s 3-STATE bus-driving outputs s Full parallel-access for loading s Buffered control inputs s P-N-P inputs reduce D-C loading on data lines Ordering Code: Order Number Package Number Package Description DM74LS373WM M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide DM74LS373SJ M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide DM74LS373N N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide DM74LS374WM M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide DM74LS374SJ M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide DM74LS374N N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. 2001 Fairchild Semiconductor Corporation DS006431 DM74LS373 • DM74LS374 Connection Diagrams DM74LS373 DM74LS374 Function Tables DM74LS373 Output Enable Control Logic Diagrams DM74LS373 Transparent Latches Output H L Q0 Z DM74LS374 Output Clock Output Control H = HIGH Level Steady State L = LOW Level Steady State X = Don’t Care Z = High Impedance State = Transition from LOW-to-HIGH level Q0 = The level of the output before steady-state input conditions were established. DM74LS374 Positive-Edge-Triggered Flip-Flops DM74LS373 • DM74LS374 Absolute Maximum Ratings Note 1 Supply Voltage Input Voltage Storage Temperature Range −65°C to +150°C Operating Free Air Temperature Range 0°C to +70°C Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. DM74LS373 Recommended Operating Conditions Parameter Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage

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DM74LS373
• DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops

DM74LS373
• DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops

These 8-bit registers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight latches of the DM74LS373 are transparent Dtype latches meaning that while the enable G is HIGH the Q outputs will follow the data D inputs. When the enable is taken LOW the output will be latched at the level of the data that was set up.

The eight flip-flops of the DM74LS374 are edge-triggered D-type flip flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D inputs.

A buffered output control input can be used to place the eight outputs in either a normal logic state HIGH or LOW logic levels or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significantly.

The output control does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered even while the outputs are OFF.
s Choice of 8 latches or 8 D-type flip-flops in a single package
s 3-STATE bus-driving outputs s Full parallel-access for loading s Buffered control inputs s P-N-P inputs reduce D-C loading on data lines
Ordering Code:

Order Number Package Number

Package Description

DM74LS373WM

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide

DM74LS373SJ

M20D
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide

DM74LS373N

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide

DM74LS374WM

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide

DM74LS374SJ

M20D
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide

DM74LS374N

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
2001 Fairchild Semiconductor Corporation DS006431

DM74LS373
• DM74LS374

Connection Diagrams

DM74LS373

DM74LS374

Function Tables

DM74LS373

Output

Enable

Control

Logic Diagrams

DM74LS373 Transparent Latches

Output

H L Q0 Z

DM74LS374

Output

Clock

Output

Control

H = HIGH Level Steady State

L = LOW Level Steady State

X = Don’t Care

Z = High Impedance State
= Transition from LOW-to-HIGH level

Q0 = The level of the output
before steady-state input conditions were established.

DM74LS374 Positive-Edge-Triggered Flip-Flops

DM74LS373
• DM74LS374

Absolute Maximum Ratings Note 1

Supply Voltage

Input Voltage

Storage Temperature Range
−65°C to +150°C

Operating Free Air Temperature Range 0°C to +70°C

Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

DM74LS373 Recommended Operating Conditions

Parameter

Supply Voltage

HIGH Level Input Voltage

LOW Level Input Voltage

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived DM74LS373WM Datasheet file may be downloaded here without warranties.

Datasheet ID: DM74LS373WM 513798