DM74LS175N
DM74LS175N Datasheet
DM74LS174<br>• DM74LS175 Hex/Quad D-Type Flip-Flops with Clear
| Part | Datasheet |
|---|---|
DM74LS175N |
DM74LS175N (pdf) |
| Related Parts | Information |
|---|---|
DM74LS174M |
DM74LS174M |
DM74LS174N |
DM74LS174N |
| PDF Datasheet Preview |
|---|
| DM74LS174 • DM74LS175 Hex/Quad D-Type Flip-Flops with Clear DM74LS174 • DM74LS175 Hex/Quad D-Type Flip-Flops with Clear These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the quad 175 versions feature complementary outputs from each flip-flop. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect at the output. s DM74LS174 contains six flip-flops with single-rail outputs s DM74LS175 contains four flip-flops with double-rail outputs s Buffered clock and direct clear inputs s Individual data input to each flip-flop s Applications include: Buffer/storage registers Shift registers Pattern generators s Typical clock frequency 40 MHz s Typical power dissipation per flip-flop 14 mW Ordering Code: Order Number Package Number Package Description DM74LS174M M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow DM74LS174SJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide DM74LS174N N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide DM74LS175M M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow DM74LS175SJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide DM74LS175N N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams DM74LS174 DM74LS175 2000 Fairchild Semiconductor Corporation DS006404 DM74LS174 • DM74LS175 Function Table Each Flip-Flop Inputs Clear Clock H = HIGH Level steady state L = LOW Level steady state X = Don’t Care = Transition from LOW-to-HIGH level Q0 = The level of Q before the indicated steady-state input conditions were established. † = DM74LS175 only Logic Diagrams Outputs Q† DM74LS174 DM74LS175 DM74LS174 • DM74LS175 Absolute Maximum Ratings Note 1 Supply Voltage Input Voltage Operating Free Air Temperature Range 0°C to +70°C Storage Temperature Range −65°C to +150°C Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. DM74LS174 Recommended Operating Conditions Parameter Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current fCLK Clock Frequency Note 2 fCLK Clock Frequency Note 3 Pulse Width Clock Note 4 Clear Data Setup Time Note 4 |
| More datasheets: SCD4LDBEIGE110AC | SCD4BEIGE | SCD4LDBEIGE24DC | SCD4DBEIGE | DM74AS00MX | DM74AS00N | DM74AS00M | IMPEXPLORER KIT | DM74LS174M | DM74LS174N |
Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived DM74LS175N Datasheet file may be downloaded here without warranties.