DM74LS164N

DM74LS164N Datasheet

DM74LS164 8-Bit Serial In/Parallel Out Shift Register

Part	Datasheet
DM74LS164N	DM74LS164N (pdf)

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DM74LS164 8-Bit Serial In/Parallel Out Shift Register DM74LS164 8-Bit Serial In/Parallel Out Shift Register These 8-bit shift registers feature gated serial inputs and an asynchronous clear. A low logic level at either input inhibits entry of the new data, and resets the first flip-flop to the low level at the next clock pulse, thus providing complete control over incoming data. A high logic level on either input enables the other input, which will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is HIGH or LOW, but only information meeting the setup and hold time requirements will be entered. Clocking occurs on the LOW-to-HIGH level transition of the clock input. All inputs are diode-clamped to minimize transmission-line effects. s Gated enable/disable serial inputs s Fully buffered clock and serial inputs s Asynchronous clear s Typical clock frequency 36 MHz s Typical power dissipation 80 mW Ordering Code: Order Number Package Number Package Description DM74LS164M M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, Narrow DM74LS164N N14A 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs Outputs Clear Clock A B QA QB QH X QA0 QB0 QH0 H QAn QGn L X L QAn QGn X L QAn QGn H = HIGH Level steady state L = LOW Level steady state X = Don't Care any input, including transitions = Transition from LOW-to-HIGH level QA0, QB0, QH0 = The level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were established. QAn, QGn = The level of QA or QG before the most recent transition of the clock indicates a one-bit shift. 2000 Fairchild Semiconductor Corporation DS006398 DM74LS164 Logic Diagram Timing Diagram DM74LS164 Absolute Maximum Ratings Note 1 Supply Voltage Input Voltage Operating Free Air Temperature Range 0°C to +70°C Storage Temperature Range −65°C to +150°C Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” tables will define the conditions for actual device operation. Recommended Operating Conditions Parameter Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current fCLK Clock Frequency Note 2 Pulse Width Clock Note 2 Clear Data Setup Time Note 2 Data Hold Time Note 2 tREL

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DM74LS164 8-Bit Serial In/Parallel Out Shift Register

DM74LS164 8-Bit Serial In/Parallel Out Shift Register

These 8-bit shift registers feature gated serial inputs and an asynchronous clear. A low logic level at either input inhibits entry of the new data, and resets the first flip-flop to the low level at the next clock pulse, thus providing complete control over incoming data. A high logic level on either input enables the other input, which will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is HIGH or LOW, but only information meeting the setup and hold time requirements will be entered. Clocking occurs on the LOW-to-HIGH level transition of the clock input. All inputs are diode-clamped to minimize transmission-line effects.
s Gated enable/disable serial inputs s Fully buffered clock and serial inputs s Asynchronous clear s Typical clock frequency 36 MHz s Typical power dissipation 80 mW
Ordering Code:

Order Number Package Number

Package Description

DM74LS164M

M14A
14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, Narrow

DM74LS164N

N14A
14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

Inputs

Outputs

Clear Clock A B QA QB QH

X QA0 QB0 QH0

H QAn QGn

L X L QAn QGn

X L QAn QGn

H = HIGH Level steady state L = LOW Level steady state X = Don't Care any input, including transitions = Transition from LOW-to-HIGH level QA0, QB0, QH0 = The level of QA, QB, or QH, respectively, before the
indicated steady-state input conditions were established.

QAn, QGn = The level of QA or QG before the most recent transition of the
clock indicates a one-bit shift.
2000 Fairchild Semiconductor Corporation DS006398

DM74LS164

Logic Diagram Timing Diagram

DM74LS164

Absolute Maximum Ratings Note 1

Supply Voltage

Input Voltage

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range
−65°C to +150°C

Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” tables will define the conditions for actual device operation.

Recommended Operating Conditions

Parameter

Supply Voltage

HIGH Level Input Voltage

LOW Level Input Voltage

HIGH Level Output Current

LOW Level Output Current
fCLK

Clock Frequency Note 2

Pulse Width

Clock

Note 2

Clear

Data Setup Time Note 2

Data Hold Time Note 2
tREL

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Datasheet ID: DM74LS164N 513771