DM74AS163N

DM74AS163N Datasheet

DM74AS161, Synchronous 4-Bit Counter with Asynchronous Clear DM74AS163, Synchronous 4-Bit Counter

Part	Datasheet
DM74AS163N	DM74AS163N (pdf)

Related Parts	Information
DM74AS161N	DM74AS161N
DM74AS161M	DM74AS161M
DM74AS163MX	DM74AS163MX
DM74AS163M	DM74AS163M

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DM74AS161, Synchronous 4-Bit Counter with Asynchronous Clear DM74AS163, Synchronous 4-Bit Counter DM74AS161, Synchronous 4-Bit Counter with Asynchronous Clear DM74AS163, Synchronous 4-Bit Counter • Switching specifications at 50pF • Switching specifications guaranteed over full temperature and VCC range • Advanced oxide-isolated, ion-implanted Schottky TTL process • Functionally and pin-for-pin compatible with Schottky and low power Schottky TTL counterpart • Improved AC performance over Schottky and low power Schottky counterparts • Synchronously programmable • Internal look ahead for fast counting • Carry output for n-bit cascading • Synchronous counting • Load control line • ESD inputs June 2007 These synchronous presettable counters feature an internal carry look ahead for application in high speed counting designs. The DM74AS161 and DM74AS163 are 4-bit binary counters. The DM74AS161 clear asynchronously, while the DM74AS163 clear synchronously. The carry output is decoded to prevent spikes during normal counting mode of operation. Synchronous operation is provided by having all flip-flops clocked simultaneously so that outputs change coincident with each other when so instructed by count enable inputs and internal gating. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous ripple clock counters. A buffered clock input triggers the four flip-flops on the rising positive-going edge of the clock input waveform. These counters are fully programmable, that is, the outputs may each be preset to either level. As presetting is synchronous, setting up a low level at the LOAD input disables the counter and causes the outputs to agree with set up data after the next clock pulse regardless of the levels of enable input. LOW-to-HIGH transitions at the LOAD input are perfectly acceptable regardless of the logic levels on the clock or enable inputs. The DM74AS161 clear function is asynchronous. A low level at the clear input sets all four of the flip-flop outputs LOW regardless of the levels of clock, load or enable inputs. This counter is provided with a clear on power-up feature. The DM74AS163 clear function is synchronous and a low level at the clear input sets all four of the flipflop outputs LOW after the next clock pulse, regardless of the levels of enable inputs. This synchronous clear allows the count length to be modified easily, as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to all LOW outputs. LOW-to-HIGH transitions at the clear input of the DM74AS163 is also permissible regardless of the levels of logic on the clock, enable or load inputs. The carry look ahead circuitry provides for cascading counters for n bit synchronous application without additional gating. Instrumental in accomplishing this function are two count-enable inputs P and T and a ripple carry output. Both count-enable inputs must be HIGH to count. The T input is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high level output pulse with a duration approximately equal to the high level portion of QA output. This high level overflow ripple carry pulse can be used to enable successive cascaded stages. HIGH-to-LOW level transitions at the enable P or T inputs of the DM74AS161 and DM74AS163, may occur regardless of the logic level on the clock. The DM74AS161 and DM74AS163 feature a fully independent clock circuit. Changes made to control inputs enable P or T, or load that will modify the operating mode will have no effect until clocking occurs. The function of the counter whether enabled, disabled, loading or counting will be dictated solely by the conditions meeting the stable set-up and hold times. DM74AS161, Synchronous 4-Bit Counter with Asynchronous Clear DM74AS163, Synchronous 4-Bit Counter Ordering Information Order Number DM74AS161M DM74AS163M Package Number M16A Package Description 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering number. Connection Diagram 1984 Fairchild Semiconductor Corporation DM74AS161, Synchronous 4-Bit Counter with Asynchronous Clear DM74AS163, Synchronous 4-Bit Counter Logic Diagrams DM74AS161 1984 Fairchild Semiconductor Corporation DM74AS161, Synchronous 4-Bit Counter with Asynchronous Clear DM74AS163, Synchronous 4-Bit Counter Logic Diagrams Continued DM74AS163 1984 Fairchild Semiconductor Corporation DM74AS161, Synchronous 4-Bit Counter with Asynchronous Clear DM74AS163, Synchronous 4-Bit Counter Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. VCC VI TA TSTG JA Parameter Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Typical Thermal Resistance Rating 7V 0°C to +70°C to +150°C 101.0°C/W Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Parameter VCC Supply Voltage VIH HIGH Level Input Voltage VIL LOW Level Input Voltage IOH HIGH Level Output Current IOL LOW Level Output Current fCLK Clock Frequency tSETUP, Set-Up Time Data A, B, C, D En P, En T LOAD CLEAR Only for DM74AS163 HIGH Set-up 1 Only for DM74AS161 CLEAR tHOLD, Hold Time Data A, B, C, D En P, En T LOAD CLEAR Only for DM74AS163 Hold 0 Only for DM74AS161 CLEAR tWCLK tWCLR Width of Clock Pulse Width of Clear Pulse, DM74ASAS161 LOW

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DM74AS161, Synchronous 4-Bit Counter with Asynchronous Clear DM74AS163, Synchronous 4-Bit Counter

DM74AS161, Synchronous 4-Bit Counter with Asynchronous Clear DM74AS163, Synchronous 4-Bit Counter
• Switching specifications at 50pF
• Switching specifications guaranteed over full
temperature and VCC range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin-for-pin compatible with Schottky
and low power Schottky TTL counterpart
• Improved AC performance over Schottky and low
power Schottky counterparts
• Synchronously programmable
• Internal look ahead for fast counting
• Carry output for n-bit cascading
• Synchronous counting
• Load control line
• ESD inputs

June 2007

These synchronous presettable counters feature an internal carry look ahead for application in high speed counting designs. The DM74AS161 and DM74AS163 are 4-bit binary counters. The DM74AS161 clear asynchronously, while the DM74AS163 clear synchronously. The carry output is decoded to prevent spikes during normal counting mode of operation. Synchronous operation is provided by having all flip-flops clocked simultaneously so that outputs change coincident with each other when so instructed by count enable inputs and internal gating. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous ripple clock counters. A buffered clock input triggers the four flip-flops on the rising positive-going edge of the clock input waveform.

These counters are fully programmable, that is, the outputs may each be preset to either level. As presetting is synchronous, setting up a low level at the LOAD input disables the counter and causes the outputs to agree with set up data after the next clock pulse regardless of the levels of enable input. LOW-to-HIGH transitions at the LOAD input are perfectly acceptable regardless of the logic levels on the clock or enable inputs.

The DM74AS161 clear function is asynchronous. A low level at the clear input sets all four of the flip-flop outputs LOW regardless of the levels of clock, load or enable inputs. This counter is provided with a clear on power-up feature. The DM74AS163 clear function is synchronous and a low level at the clear input sets all four of the flipflop outputs LOW after the next clock pulse, regardless
of the levels of enable inputs. This synchronous clear allows the count length to be modified easily, as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to all LOW outputs. LOW-to-HIGH transitions at the clear input of the DM74AS163 is also permissible regardless of the levels of logic on the clock, enable or load inputs.

The carry look ahead circuitry provides for cascading counters for n bit synchronous application without additional gating. Instrumental in accomplishing this function are two count-enable inputs P and T and a ripple carry output. Both count-enable inputs must be HIGH to count. The T input is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high level output pulse with a duration approximately equal to the high level portion of QA output. This high level overflow ripple carry pulse can be used to enable successive cascaded stages. HIGH-to-LOW level transitions at the enable P or T inputs of the DM74AS161 and DM74AS163, may occur regardless of the logic level on the clock.

The DM74AS161 and DM74AS163 feature a fully independent clock circuit. Changes made to control inputs enable P or T, or load that will modify the operating mode will have no effect until clocking occurs. The function of the counter whether enabled, disabled, loading or counting will be dictated solely by the conditions meeting the stable set-up and hold times.

DM74AS161, Synchronous 4-Bit Counter with Asynchronous Clear DM74AS163, Synchronous 4-Bit Counter
Ordering Information

Order Number

DM74AS161M DM74AS163M

Package Number

M16A

Package Description 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering number.

Connection Diagram
1984 Fairchild Semiconductor Corporation

DM74AS161, Synchronous 4-Bit Counter with Asynchronous Clear DM74AS163, Synchronous 4-Bit Counter

Logic Diagrams

DM74AS161
1984 Fairchild Semiconductor Corporation

DM74AS161, Synchronous 4-Bit Counter with Asynchronous Clear DM74AS163, Synchronous 4-Bit Counter

Logic Diagrams Continued

DM74AS163
1984 Fairchild Semiconductor Corporation

DM74AS161, Synchronous 4-Bit Counter with Asynchronous Clear DM74AS163, Synchronous 4-Bit Counter

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

VCC VI TA TSTG JA

Parameter Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Typical Thermal Resistance

Rating 7V
0°C to +70°C to +150°C
101.0°C/W

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.

Parameter

VCC Supply Voltage

VIH HIGH Level Input Voltage

VIL LOW Level Input Voltage

IOH HIGH Level Output Current

IOL LOW Level Output Current
fCLK Clock Frequency
tSETUP, Set-Up Time

Data A, B, C, D En P, En T

LOAD

CLEAR

Only for DM74AS163 HIGH

Set-up 1 Only for DM74AS161 CLEAR
tHOLD, Hold Time

Data A, B, C, D En P, En T

LOAD

CLEAR Only for DM74AS163

Hold 0 Only for DM74AS161 CLEAR
tWCLK tWCLR

Width of Clock Pulse Width of Clear Pulse, DM74ASAS161 LOW

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Datasheet ID: DM74AS163N 513716