DM74ALS646WM

DM74ALS646WM Datasheet

DM74ALS646 Octal 3-STATE Bus Transceiver and Register

Part	Datasheet
DM74ALS646WM	DM74ALS646WM (pdf)

Related Parts	Information
DM74ALS646NT	DM74ALS646NT
DM74ALS646WMX	DM74ALS646WMX

PDF Datasheet Preview
DM74ALS646 Octal 3-STATE Bus Transceiver and Register DM74ALS646 Octal 3-STATE Bus Transceiver and Register This device incorporates an octal bus transceiver and an octal D-type register configured to enable multiplexed transmission of data from bus to bus or internal register to bus. This bus transceiver features totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic level drive provides this device with the capability of being connected directly to and driving the bus lines in a bus-organized system without the need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The registers in the DM74ALS646 are edge-triggered Dtype flip-flops. On the positive transition of the clock CAB or CBA , the input bus data is stored into the appropriate register. The CAB input controls the transfer of data into the A register and the CBA input controls the B register. The SAB and SBA control pins are provided to select whether real-time data or stored data is transferred. A LOW input level selects real-time data, and a HIGH level selects stored data. The select controls have a “make before break” configuration to eliminate a glitch which would normally occur in a typical multiplexer during the transition between store and real-time data. The enable G and direction control pins provide four modes of operation real-time data transfer from bus A to B, realtime data transfer from bus B to A, real-time bus A and/or B data transfer to internal storage, or internally stored data transfer to bus A or B. When the enable G pin is LOW, the direction pin selects which bus receives data. When the enable G pin is HIGH, both buses become disabled yet their input function is still enabled. s Switching specifications at 50 pF s Switching specifications guaranteed over full tempera- ture and VCC range s Advanced oxide-isolated, ion-implanted Schottky TTL process s 3-STATE buffer outputs drive bus lines directly s Multiplexed real-time and stored data s Independent registers for A and B buses Ordering Code Order Number Package Number Package Description DM74ALS646WM M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide DM74ALS646NT N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. 2001 Fairchild Semiconductor Corporation DS009172 DM74ALS646 Connection Diagram Function Table Inputs Data I/O Note 1 G DIR CAB CBA SAB SBA A1 thru A8 B1 thru B8 Operation or Function Input Not Specified Store A, B Unspecified X Not Specified Input Store B, A Unspecified Input Input Store A and B Data H X H/L H/L X Input Input Isolation, Hold Storage L LXXXL Output Input Real-Time B Data to a Bus L X H/L X H Output Input Stored B Data to a Bus L HXX L X Input Output Real-Time A Data to B Bus L H/L X H X Input Output Stored A Data to B Bus H = HIGH Logic Level L = LOW Logic Level X = Don’t Care Either LOW or HIGH Logic Levels including transitions H/L = Either LOW or HIGH Logic Level excluding transitions = Positive going edge of pulse Note 1 The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. Logic Diagram DM74ALS646 Absolute Maximum Ratings Note 2 Supply Voltage Input Voltage

PDF Datasheet Preview

DM74ALS646 Octal 3-STATE Bus Transceiver and Register

DM74ALS646 Octal 3-STATE Bus Transceiver and Register

This device incorporates an octal bus transceiver and an octal D-type register configured to enable multiplexed transmission of data from bus to bus or internal register to bus.

This bus transceiver features totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic level drive provides this device with the capability of being connected directly to and driving the bus lines in a bus-organized system without the need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The registers in the DM74ALS646 are edge-triggered Dtype flip-flops. On the positive transition of the clock CAB or CBA , the input bus data is stored into the appropriate register. The CAB input controls the transfer of data into the A register and the CBA input controls the B register.

The SAB and SBA control pins are provided to select whether real-time data or stored data is transferred. A LOW input level selects real-time data, and a HIGH level selects stored data. The select controls have a “make before break” configuration to eliminate a glitch which would normally occur in a typical multiplexer during the transition between store and real-time data.

The enable G and direction control pins provide four modes of operation real-time data transfer from bus A to B, realtime data transfer from bus B to A, real-time bus A and/or B data transfer to internal storage, or internally stored data transfer to bus A or B.

When the enable G pin is LOW, the direction pin selects which bus receives data. When the enable G pin is HIGH, both buses become disabled yet their input function is still enabled.
s Switching specifications at 50 pF s Switching specifications guaranteed over full tempera-
ture and VCC range s Advanced oxide-isolated, ion-implanted Schottky TTL
process s 3-STATE buffer outputs drive bus lines directly s Multiplexed real-time and stored data s Independent registers for A and B buses
Ordering Code

Order Number Package Number

Package Description

DM74ALS646WM

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide

DM74ALS646NT

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
2001 Fairchild Semiconductor Corporation DS009172

DM74ALS646

Connection Diagram

Function Table

Inputs

Data I/O Note 1

G DIR CAB CBA SAB SBA A1 thru A8 B1 thru B8

Operation or Function

Input

Not Specified Store A, B Unspecified

X Not Specified

Input

Store B, A Unspecified

Input

Input

Store A and B Data

H X H/L H/L X

Input

Input

Isolation, Hold Storage

L LXXXL

Output

Input

Real-Time B Data to a Bus

L X H/L X H

Output

Input

Stored B Data to a Bus

L HXX L X

Input

Output Real-Time A Data to B Bus

L H/L X H X

Input

Output Stored A Data to B Bus

H = HIGH Logic Level L = LOW Logic Level X = Don’t Care Either LOW or HIGH Logic Levels including transitions H/L = Either LOW or HIGH Logic Level excluding transitions = Positive going edge of pulse

Note 1 The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.

Logic Diagram

DM74ALS646

Absolute Maximum Ratings Note 2

Supply Voltage Input Voltage

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Datasheet ID: DM74ALS646WM 513700