DM74ALS109AMX
DM74ALS109AMX Datasheet
DM74ALS109A Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and Clear
| Part | Datasheet |
|---|---|
DM74ALS109AMX |
DM74ALS109AMX (pdf) |
| Related Parts | Information |
|---|---|
|
DM74ALS109AM |
DM74ALS109AM |
DM74ALS109AN |
DM74ALS109AN |
| PDF Datasheet Preview |
|---|
| DM74ALS109A Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and Clear DM74ALS109A Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and Clear The DM74ALS109A is a dual edge-triggered flip-flop. Each flip-flop has individual J, K, clock, clear and preset inputs, and also complementary Q and Q outputs. Information at input J or K is transferred to the Q output on the positive going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive going pulse. When the clock input is at either the HIGH or LOW level, the J, K input signal has no effect. Asynchronous preset and clear inputs will set or clear Q output respectively upon the application of low level signal. The J-K design allows operation as a D flip-flop by tying the J and K inputs together. s Switching specifications at 50 pF s Switching specifications guaranteed over full tempera- ture and VCC range s Advanced oxide-isolated, ion-implanted Schottky TTL process s Functionally and pin for pin compatible with Schottky and LS TTL counterpart s Improved AC performance over LS109 at approximately half the power Ordering Code: Order Number Package Number Package Description DM74ALS109AM M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow DM74ALS109AN N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs Outputs PR CLR CK J K LHXXX HL XXX L X H Note 1 H Note 1 TOGGLE HH LH HH L XX L = LOW State H = HIGH State X = Don't Care = Positive Edge Transition, Q0 = Previous Condition of Q Note 1 This condition is nonstable it will not persist when present and clear inputs return to their inactive HIGH level. The output levels in this condition are not guaranteed to meet the VOH specification. 2000 Fairchild Semiconductor Corporation DS006196 DM74ALS109A Logic Diagram DM74ALS109A Absolute Maximum Ratings Note 2 Supply Voltage Input Voltage Operating Free Air Temperature Range 0°C to +70°C Storage Temperature Range −65°C to +150°C Typical N Package 82.5°C/W M Package 111.5°C/W Note 2 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Recommended Operating Conditions VCC VIH VIL IOH IOL fCLK tW CLK Parameter Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Clock Frequency Pulse Width Clock HIGH Clock LOW |
| More datasheets: L6R60D-360-C6 | L6R60D-090-C14 | L6R60D-180-C8 | L6R60D-420-C8 | L6R60D-420-C6 | L6R60D-480-C6 | L6R60D-090-C8 | L6R60D-420-C14 | L6R60D-480-C8 | DFR0250 |
Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived DM74ALS109AMX Datasheet file may be downloaded here without warranties.