CGS3313M
CGS3313M Datasheet
CGS3311<br>• CGS3312<br>• CGS3313<br>• CGS3314<br>• CGS3315<br>• CGS3316<br>• CGS3317<br>• CGS3318<br>• CGS3319 CMOS Crystal Clock Generators
| Part | Datasheet |
|---|---|
CGS3313M |
CGS3313M (pdf) |
| Related Parts | Information |
|---|---|
|
CGS3319MX |
CGS3319MX |
|
CGS3313MX |
CGS3313MX |
|
CGS3311MX |
CGS3311MX |
|
CGS3318M |
CGS3318M |
|
CGS3312MX |
CGS3312MX |
|
CGS3318MX |
CGS3318MX |
|
CGS3314MX |
CGS3314MX |
|
CGS3315MX |
CGS3315MX |
|
CGS3316MX |
CGS3316MX |
|
CGS3319M |
CGS3319M |
|
CGS3314M |
CGS3314M |
|
CGS3317MX |
CGS3317MX |
|
CGS3311M |
CGS3311M |
|
CGS3312M |
CGS3312M |
| PDF Datasheet Preview |
|---|
| CGS3311 • CGS3312 • CGS3313 • CGS3314 • CGS3315 • CGS3316 • CGS3317 • CGS3318 • CGS3319 CMOS Crystal Clock Generators CGS3311 • CGS3312 • CGS3313 • CGS3314 • CGS3315 • CGS3316 • CGS3317 • CGS3318 • CGS3319 CMOS Crystal Clock Generators The CGS3311, CGS3312, CGS3313, CGS3314, CGS3315, CGS3316, CGS3317, CGS3318 and CGS3319 devices are designed for Clock Generation and Support CGS applications up to 110 MHz. The CGS331x series of devices are crystal controlled CMOS oscillators requiring a minimum of external components. The 331x devices provide selectable output divide ratio and selectable crystal drive level . The circuit is designed to operate over a wide frequency range using fundamental model or overtone crystals. s Fairchild’s CGS family of devices for high frequency clock source applications s Crystal frequency operation range fundamental 10 MHz to 100 MHz typical 3rd or 5th overtone 10 MHz to 85 MHz s Programmable oscillator drive s Selectable fast output edge rates s Output symmetry circuit to adjust 50% duty cycle point between CMOS and TTL levels s Output current drive of 48 mA for IOL/IOH s FACT CMOS output levels s Output has high speed short circuit protection s Basic oscillator type Pierce s Hysteresis inputs to improve noise margin Ordering Code: Order Number Package Number Package Description CGS3311M M08A 8-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow Body CGS3312M M08A 8-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow Body CGS3313M M08A 8-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow Body CGS3314M M08A 8-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow Body CGS3315M M08A 8-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow Body CGS3316M M08A 8-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow Body CGS3317M M08A 8-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow Body CGS3318M M08A 8-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow Body CGS3319M M08A 8-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow Body Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. FACT is a trademark of Fairchild Semiconductor Corporation. 1999 Fairchild Semiconductor Corporation DS010980.prf CGS3311 • CGS3312 • CGS3313 • CGS3314 • CGS3315 • CGS3316 • CGS3317 • CGS3318 • CGS3319 Connection Diagrams A 3311 B 3312 C 3313 E 3315 F 3316 G 3317 D 3314 H 3318 I 3319 CGS3311 • CGS3312 • CGS3313 • CGS3314 • CGS3315 • CGS3316 • CGS3317 • CGS3318 • CGS3319 Truth Tables Division Selection DIVB DIVA OEL F 0/F X 0/F 0 0/F 0 OEH X 1 X Divider Output Divide-by 1 Divide-by 2 Divide-by 4 Divide-by 8 Divide-by 16 Divide-by 32 Output Reset HIGH at Re-enable Output Reset HIGH at Re-enable Note Actual value of the floating OSC_DR and DIVB input is VCC/2 Pin Descriptions Rise and Fall Time Selection OSC_DR DIV TRF Rise/Fall Time ns N 0/F 2 N 1 less than 2 Y 0/F 4 X 0/F 4 Drive Selection OSC_DR 0 1 F Drive Low Medium High Note Where “F” indicates floating the input. Note Pin out varies for each device. OSC_IN Input to Oscillator Inverter. The output of the crystal would be connected here. OSC_OUT Resistive Buffered Output of the Oscillator Inverter OSC_DR 3 Level input pin that selects Oscillator Drive OUT Level DIVA Input used to select Binary Divide-by Option. OSCLO_1 This pin has CMOS compatible input levels. Active HIGH 3-STATE enable pin. This pin pulls OSCLO_2 to a high value when left floating and 3-STATEs the output when forced low. This pin has TTL compatible input levels. VCC GND Active LOW 3-STATE enable pin. This pin pulls to a low value when left floating and 3-STATE the output when forced HIGH. This pin has TTL compatible input levels. Rise and Fall time override pin. Available only for die form. This pin is the main clock output on the device. |
| More datasheets: CGS3312MX | CGS3318MX | CGS3314MX | CGS3315MX | CGS3316MX | CGS3319M | CGS3314M | CGS3317MX | CGS3311M | CGS3312M |
Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CGS3313M Datasheet file may be downloaded here without warranties.