CD4541BCN

CD4541BCN Datasheet

CD4541BC Programmable Timer

Part	Datasheet
CD4541BCN	CD4541BCN (pdf)

Related Parts	Information
CD4541BCM	CD4541BCM
CD4541BCMX	CD4541BCMX

PDF Datasheet Preview
CD4541BC Programmable Timer CD4541BC Programmable Timer The CD4541BC Programmable Timer is designed with a 16-stage binary counter, an integrated oscillator for use with an external capacitor and two resistors, output control logic, and a special power-on reset circuit. The special features of the power-on reset circuit are first, no additional static power consumption and second, the part functions across the full voltage range whether power-on reset is enabled or disabled. Timing and the counter are initialized by turning on power, if the power-on reset is enabled. When the power is already on, an external reset pulse will also initialize the timing and counter. After either reset is accomplished, the oscillator frequency is determined by the external RC network. The 16-stage counter divides the oscillator frequency by any of 4 digitally controlled division ratios. s Available division ratios 28, 210, 213, or 216 s Increments on positive edge clock transitions s Built-in low power RC oscillator ±2% accuracy over temperature range and ±10% supply and ±3% over processing < 10 kHz s Oscillator frequency range DC to 100 kHz s Oscillator may be bypassed if external clock is available apply external clock to pin 3 s Automatic reset initializes all counters when power turns on s External master reset totally independent of automatic reset operation s Operates at 2n frequency divider or single transition timer s Q/Q select provides output logic level flexibility s Reset auto or master disables oscillator during reset- ting to provide no active power dissipation s Clock conditioning circuit permits operation with very slow clock rise and fall times s Wide supply voltage to 15V s High noise VDD typ. s parameter ratings s Symmetrical output characteristics s Maximum input leakage 1 µA at 15V over full tempera- ture range s High output drive pin 8 min. one TTL load Ordering Code: Order Number Package Number Package Description CD4541BCM M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow CD4541BCN N14A 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram connected Top View 2002 Fairchild Semiconductor Corporation DS006001 CD4541BC Truth Table State 5 Auto Reset Operating Auto Reset Disabled 6 Timer Operational Master Reset On 9 Output Initially Low Output Initially High after Reset after Reset 10 Single Cycle Mode Recycle Mode Division Ratio Table Number of Counter Stages Count 2n 8192 1024 256 65536 Operating Characteristics With Auto Reset pin set to a “0” the counter circuit is initialized by turning on power. Or with power already on, the counter circuit is reset when the Master Reset pin is set to a Both types of reset will result in synchronously resetting all counter stages independent of counter state. The RC oscillator frequency is determined by the external RC network, i.e.: and RS 2 Rtc where RS 10 The time select inputs A and B provide a two-bit address to output any one of four counter stages 28, 210, 213, and The 2n counts as shown in the Division Ratio Table represent the Q output of the Nth stage of the counter. When A is “1”, 216 is selected for both states of B. However, when B is “0”, normal counting is interrupted and the 9th counter stage receives its clock directly from the oscillator i.e., effectively outputting The Q/Q select output control pin provides for a choice of output level. When the counter is in a reset condition and Q/Q select pin is set to a “0” the Q output is a Correspondingly, when Q/Q select pin is set to a “1” the Q output is a When the mode control pin is set to a “1”, the selected count is continually transmitted to the output. But, with mode pin “0” and after a reset condition the RS flip-flop resets see Logic Diagram , counting commences and after 2n−1 counts the RS flip-flop sets which causes the output to change state. Hence, after another 2n−1 counts the output will not change. Thus, a Master Reset pulse must be applied or a change in the mode pin level is required to reset the single cycle operation. Typical RC Oscillator Characteristics RC Oscillator Frequency as a Function of RTC and C Solid Line = RTC = 56 RS = 1 and C = 1000 pF f = kHz VDD = 10V and TA = 25° Dashed Line = RTC = 56 RS = 120 and C = 1000 pF f = kHz VDD = 10V and TA = 25° Line A f as a function of C and RTC = 56 RS = 120k Line B f as a function of RTC and C = 100 pF RS = 2 RTC CD4541BC Operating Characteristics Continued Oscillator Circuit Using RC Configuration Logic Diagram VDD = Pin 14 VSS = Pin 7 CD4541BC Absolute Maximum Ratings Note 1 Note 2

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CD4541BC Programmable Timer

CD4541BC Programmable Timer

The CD4541BC Programmable Timer is designed with a 16-stage binary counter, an integrated oscillator for use with an external capacitor and two resistors, output control logic, and a special power-on reset circuit. The special features of the power-on reset circuit are first, no additional static power consumption and second, the part functions across the full voltage range whether power-on reset is enabled or disabled.

Timing and the counter are initialized by turning on power, if the power-on reset is enabled. When the power is already on, an external reset pulse will also initialize the timing and counter. After either reset is accomplished, the oscillator frequency is determined by the external RC network. The 16-stage counter divides the oscillator frequency by any of 4 digitally controlled division ratios.
s Available division ratios 28, 210, 213, or 216 s Increments on positive edge clock transitions s Built-in low power RC oscillator ±2% accuracy over
temperature range and ±10% supply and ±3% over processing < 10 kHz s Oscillator frequency range DC to 100 kHz s Oscillator may be bypassed if external clock is available apply external clock to pin 3 s Automatic reset initializes all counters when power turns on s External master reset totally independent of automatic reset operation
s Operates at 2n frequency divider or single transition timer
s Q/Q select provides output logic level flexibility s Reset auto or master disables oscillator during reset-
ting to provide no active power dissipation s Clock conditioning circuit permits operation with very
slow clock rise and fall times s Wide supply voltage to 15V s High noise VDD typ. s parameter ratings s Symmetrical output characteristics s Maximum input leakage 1 µA at 15V over full tempera-
ture range s High output drive pin 8 min. one TTL load
Ordering Code:

Order Number Package Number

Package Description

CD4541BCM

M14A
14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow

CD4541BCN

N14A
14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram
connected

Top View
2002 Fairchild Semiconductor Corporation DS006001

CD4541BC

Truth Table

State
5 Auto Reset Operating Auto Reset Disabled
6 Timer Operational

Master Reset On
9 Output Initially Low

Output Initially High
after Reset
after Reset
10 Single Cycle Mode

Recycle Mode

Division Ratio Table

Number of

Counter Stages

Count 2n
8192 1024 256 65536

Operating Characteristics

With Auto Reset pin set to a “0” the counter circuit is initialized by turning on power. Or with power already on, the counter circuit is reset when the Master Reset pin is set to a Both types of reset will result in synchronously resetting all counter stages independent of counter state. The RC oscillator frequency is determined by the external RC network, i.e.:
and RS 2 Rtc where RS 10 The time select inputs A and B provide a two-bit address to output any one of four counter stages 28, 210, 213, and The 2n counts as shown in the Division Ratio Table represent the Q output of the Nth stage of the counter. When A is “1”, 216 is selected for both states of B.

However, when B is “0”, normal counting is interrupted and the 9th counter stage receives its clock directly from the oscillator i.e., effectively outputting

The Q/Q select output control pin provides for a choice of output level. When the counter is in a reset condition and Q/Q select pin is set to a “0” the Q output is a Correspondingly, when Q/Q select pin is set to a “1” the Q output is a

When the mode control pin is set to a “1”, the selected count is continually transmitted to the output. But, with mode pin “0” and after a reset condition the RS flip-flop resets see Logic Diagram , counting commences and after 2n−1 counts the RS flip-flop sets which causes the output to change state. Hence, after another 2n−1 counts the output will not change. Thus, a Master Reset pulse must be applied or a change in the mode pin level is required to reset the single cycle operation.

Typical RC Oscillator Characteristics

RC Oscillator Frequency as a Function of RTC and C

Solid Line = RTC = 56 RS = 1 and C = 1000 pF f = kHz VDD = 10V and TA = 25°

Dashed Line = RTC = 56 RS = 120 and C = 1000 pF f = kHz VDD = 10V and TA = 25°

Line A f as a function of C and RTC = 56 RS = 120k Line B f as a function of RTC and C = 100 pF RS = 2 RTC

CD4541BC

Operating Characteristics Continued

Oscillator Circuit Using RC Configuration

Logic Diagram

VDD = Pin 14 VSS = Pin 7

CD4541BC

Absolute Maximum Ratings Note 1

Note 2

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Datasheet ID: CD4541BCN 513587