CD4094BCN

CD4094BCN Datasheet

CD4094BC 8-Bit Shift Register/Latch with 3-STATE Outputs

Part	Datasheet
CD4094BCN	CD4094BCN (pdf)

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CD4094BC 8-Bit Shift Register/Latch with 3-STATE Outputs CD4094BC 8-Bit Shift Register/Latch with 3-STATE Outputs The CD4094BC consists of an 8-bit shift register and a 3-STATE 8-bit latch. Data is shifted serially through the shift register on the positive transition of the clock. The output of the last stage QS can be used to cascade several devices. Data on the QS output is transferred to a second output, on the following negative clock edge. The output of each stage of the shift register feeds a latch, which latches data on the negative edge of the STROBE input. When STROBE is HIGH, data propagates through the latch to 3-STATE output gates. These gates are enabled when OUTPUT ENABLE is taken HIGH. s Wide supply voltage range 3.0V to 18V s High noise immunity VDD typ. s Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS s 3-STATE outputs Ordering Code: Order Number Package Number Package Description CD4094BCWM M16B 16-Lead Small Outline Intergrated Circuit SOIC , JEDEC MS-013, Wide CD4094BCN N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Top View Truth Table Clock Output Strobe Data Parallel Outputs Serial Outputs Enable Note 1 Hi-Z Hi-Z Q7 No Change Hi-Z Hi-Z No Change Q7 X No Change No Change Q7 No Change QN−1 Q7 No Change QN−1 Q7 No Change 1 No Change No Change No Change Q7 X = Don't Care = HIGH-to-LOW = LOW-to-HIGH Note 1 At the positive clock edge, information in the 7th shift register stage is transferred to Q8 and QS. 2002 Fairchild Semiconductor Corporation DS005983 CD4094BC Block Diagram CD4094BC Absolute Maximum Ratings Note 2 Note 3 Supply Voltage VDD Input Voltage VIN Storage Temperature Range TS Power Dissipation PD Dual-In-Line Small Outline Lead Temperature TL Soldering, 10 seconds to +18 VDC to VDD VDC −65°C to +150°C 700 mW 500 mW 260°C Recommended Operating Conditions Note 3 DC Supply Voltage VDD to +15 VDC Input Voltage VIN

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CD4094BC 8-Bit Shift Register/Latch with 3-STATE Outputs

CD4094BC 8-Bit Shift Register/Latch with 3-STATE Outputs

The CD4094BC consists of an 8-bit shift register and a 3-STATE 8-bit latch. Data is shifted serially through the shift register on the positive transition of the clock. The output of the last stage QS can be used to cascade several devices. Data on the QS output is transferred to a second output, on the following negative clock edge.

The output of each stage of the shift register feeds a latch, which latches data on the negative edge of the STROBE input. When STROBE is HIGH, data propagates through the latch to 3-STATE output gates. These gates are enabled when OUTPUT ENABLE is taken HIGH.
s Wide supply voltage range 3.0V to 18V s High noise immunity VDD typ. s Low power TTL compatibility:

Fan out of 2 driving 74L or 1 driving 74LS s 3-STATE outputs
Ordering Code:

Order Number Package Number

Package Description

CD4094BCWM

M16B
16-Lead Small Outline Intergrated Circuit SOIC , JEDEC MS-013, Wide

CD4094BCN

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Top View

Truth Table

Clock Output Strobe Data

Parallel Outputs

Serial Outputs

Enable

Note 1

Hi-Z

Hi-Z

Q7 No Change

Hi-Z

Hi-Z No Change Q7

X No Change No Change Q7 No Change

QN−1

Q7 No Change

QN−1

Q7 No Change
1 No Change No Change No Change Q7

X = Don't Care
= HIGH-to-LOW = LOW-to-HIGH

Note 1 At the positive clock edge, information in the 7th shift register stage is transferred to Q8 and QS.
2002 Fairchild Semiconductor Corporation DS005983

CD4094BC

Block Diagram

CD4094BC

Absolute Maximum Ratings Note 2

Note 3

Supply Voltage VDD Input Voltage VIN Storage Temperature Range TS Power Dissipation PD

Dual-In-Line

Small Outline

Lead Temperature TL Soldering, 10 seconds
to +18 VDC to VDD VDC
−65°C to +150°C
700 mW 500 mW
260°C

Recommended Operating Conditions Note 3

DC Supply Voltage VDD
to +15 VDC

Input Voltage VIN

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Datasheet ID: CD4094BCN 513579