CD4053BCN

CD4053BCN Datasheet

CD4051BC<br>• CD4052BC<br>• CD4053BC Single 8-Channel Analog Multiplexer/Demultiplexer<br>• Dual 4-Channel Analog Multiplexer/Demultiplexer<br>• Triple 2-Channel Analog Multiplexer/Demultiplexer

Part	Datasheet
CD4053BCN	CD4053BCN (pdf)

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CD4053BCSJX	CD4053BCSJX
CD4053BCSJ	CD4053BCSJ
CD4052BCSJ	CD4052BCSJ
CD4051BCSJX	CD4051BCSJX
CD4053BCM	CD4053BCM
CD4052BCN	CD4052BCN
CD4051BCN	CD4051BCN
CD4051BCM	CD4051BCM
CD4052BCM	CD4052BCM
CD4051BCSJ	CD4051BCSJ
CD4051BCMTC	CD4051BCMTC
CD4051BCMTCX	CD4051BCMTCX
CD4052BCSJX	CD4052BCSJX

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CD4051BC • CD4052BC • CD4053BC Single 8-Channel Analog Multiplexer/Demultiplexer • Dual 4-Channel Analog Multiplexer/Demultiplexer • Triple 2-Channel Analog Multiplexer/Demultiplexer CD4051BC • CD4052BC • CD4053BC Single 8-Channel Analog Multiplexer/Demultiplexer • Dual 4-Channel Analog Multiplexer/Demultiplexer • Triple 2-Channel Analog Multiplexer/Demultiplexer The CD4051BC, CD4052BC, and CD4053BC analog multiplexers/demultiplexers are digitally controlled analog switches having low “ON” impedance and very low “OFF” leakage currents. Control of analog signals up to 15Vp-p can be achieved by digital signal amplitudes of 3−15V. For example, if VDD = 5V, VSS = 0V and VEE = −5V, analog signals from −5V to +5V can be controlled by digital inputs of 0−5V. The multiplexer circuits dissipate extremely low quiescent power over the full VDD−VSS and VDD−VEE supply voltage ranges, independent of the logic state of the control signals. When a logical “1” is present at the inhibit input terminal all channels are “OFF”. CD4051BC is a single 8-channel multiplexer having three binary control inputs. A, B, and C, and an inhibit input. The three binary signals select 1 of 8 channels to be turned “ON” and connect the input to the output. CD4052BC is a differential 4-channel multiplexer having two binary control inputs, A and B, and an inhibit input. The two binary input signals select 1 or 4 pairs of channels to be turned on and connect the differential analog inputs to the differential outputs. CD4053BC is a triple 2-channel multiplexer having three separate digital control inputs, A, B, and C, and an inhibit input. Each control input selects one of a pair of channels which are connected in a single-pole double-throw configuration. s Wide range of digital and analog signal levels digital 3 15V, analog to 15Vp-p s Low “ON” resistance typ. over entire 15Vp-p signal-input range for VDD − VEE = 15V s High “OFF” resistance channel leakage of ±10 pA typ. at VDD − VEE = 10V s Logic level conversion for digital addressing signals of 3 15V VDD − VSS = 3 15V to switch analog signals to 15 Vp-p VDD − VEE = 15V s Matched switch characteristics = typ. for VDD − VEE = 15V s Very low quiescent power dissipation under all digital-control input and supply conditions 1 µ W typ. at VDD − VSS = VDD − VEE = 10V s Binary address decoding on chip Ordering Code: Order Number Package Number Package Description CD4051BCM M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow CD4051BCSJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide CD4051BCMTC MTC16 16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide CD4051BCN N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide CD4052BCM M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow CD4052BCSJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide CD4052BCN N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide CD4053BCM M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow CD4053BCSJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide CD4053BCN N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. 2002 Fairchild Semiconductor Corporation DS005662 CD4051BC • CD4052BC • CD4053BC Connection Diagrams Pin Assignments for DIP and SOIC CD4051BC CD4052BC CD4053BC Truth Table INHIBIT 0 1 *Don’t Care condition. INPUT STATES “ON” CHANNELS CD4051B CD4052B CD4053B 0X, 0Y cx, bx, ax 1X, 1Y cx, bx, ay 2X, 2Y cx, by, ax 3X, 3Y cx, by, ay cy, bx, ax cy, bx, ay cy, by, ax cy, by, ay NONE NONE NONE CD4051BC • CD4052BC • CD4053BC Logic Diagrams CD4051BC CD4052BC CD4051BC • CD4052BC • CD4053BC Logic Diagrams Continued CD4053BC CD4051BC • CD4052BC • CD4053BC Absolute Maximum Ratings Note 1 DC Supply Voltage VDD Input Voltage VIN Storage Temperature Range TS Power Dissipation PD Dual-In-Line Small Outline Lead Temperature TL soldering, 10 seconds VDC to +18 VDC to VDD VDC −65°C to +150°C 700 mW 500 mW

PDF Datasheet Preview

CD4051BC
• CD4052BC
• CD4053BC Single 8-Channel Analog Multiplexer/Demultiplexer
• Dual 4-Channel Analog Multiplexer/Demultiplexer
• Triple 2-Channel Analog Multiplexer/Demultiplexer

CD4051BC
• CD4052BC
• CD4053BC

Single 8-Channel Analog Multiplexer/Demultiplexer
• Dual 4-Channel Analog Multiplexer/Demultiplexer
• Triple 2-Channel Analog Multiplexer/Demultiplexer

The CD4051BC, CD4052BC, and CD4053BC analog multiplexers/demultiplexers are digitally controlled analog switches having low “ON” impedance and very low “OFF” leakage currents. Control of analog signals up to 15Vp-p can be achieved by digital signal amplitudes of 3−15V. For example, if VDD = 5V, VSS = 0V and VEE = −5V, analog signals from −5V to +5V can be controlled by digital inputs of 0−5V. The multiplexer circuits dissipate extremely low quiescent power over the full VDD−VSS and VDD−VEE supply voltage ranges, independent of the logic state of the control signals. When a logical “1” is present at the inhibit input terminal all channels are “OFF”.

CD4051BC is a single 8-channel multiplexer having three binary control inputs. A, B, and C, and an inhibit input. The three binary signals select 1 of 8 channels to be turned “ON” and connect the input to the output.

CD4052BC is a differential 4-channel multiplexer having two binary control inputs, A and B, and an inhibit input. The two binary input signals select 1 or 4 pairs of channels to be turned on and connect the differential analog inputs to the differential outputs.

CD4053BC is a triple 2-channel multiplexer having three separate digital control inputs, A, B, and C, and an inhibit input. Each control input selects one of a pair of channels which are connected in a single-pole double-throw configuration.
s Wide range of digital and analog signal levels digital 3 15V, analog to 15Vp-p
s Low “ON” resistance typ. over entire 15Vp-p signal-input range for VDD − VEE = 15V
s High “OFF” resistance channel leakage of ±10 pA typ. at VDD − VEE = 10V
s Logic level conversion for digital addressing signals of 3 15V VDD − VSS = 3 15V to switch analog signals to 15 Vp-p VDD − VEE = 15V
s Matched switch characteristics = typ. for VDD − VEE = 15V
s Very low quiescent power dissipation under all digital-control input and supply conditions 1 µ W typ. at VDD − VSS = VDD − VEE = 10V
s Binary address decoding on chip
Ordering Code:

Order Number Package Number

Package Description

CD4051BCM

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow

CD4051BCSJ

M16D
16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide

CD4051BCMTC

MTC16
16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide

CD4051BCN

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide

CD4052BCM

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow

CD4052BCSJ

M16D
16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide

CD4052BCN

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide

CD4053BCM

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow

CD4053BCSJ

M16D
16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide

CD4053BCN

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
2002 Fairchild Semiconductor Corporation DS005662

CD4051BC
• CD4052BC
• CD4053BC

Connection Diagrams

Pin Assignments for DIP and SOIC

CD4051BC

CD4052BC

CD4053BC

Truth Table

INHIBIT 0 1
*Don’t Care condition.

INPUT STATES
“ON” CHANNELS

CD4051B CD4052B CD4053B
0X, 0Y cx, bx, ax
1X, 1Y cx, bx, ay
2X, 2Y cx, by, ax
3X, 3Y cx, by, ay
cy, bx, ax
cy, bx, ay
cy, by, ax
cy, by, ay

NONE

NONE

NONE

CD4051BC
• CD4052BC
• CD4053BC

Logic Diagrams

CD4051BC

CD4052BC

CD4051BC
• CD4052BC
• CD4053BC

Logic Diagrams Continued

CD4053BC

CD4051BC
• CD4052BC
• CD4053BC

Absolute Maximum Ratings Note 1

DC Supply Voltage VDD Input Voltage VIN Storage Temperature

Range TS Power Dissipation PD

Dual-In-Line Small Outline

Lead Temperature TL soldering, 10 seconds

VDC to +18 VDC to VDD VDC
−65°C to +150°C
700 mW 500 mW

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Datasheet ID: CD4053BCN 513572