CD4027BCN

CD4027BCN Datasheet

CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset

Part	Datasheet
CD4027BCN	CD4027BCN (pdf)

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CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset The CD4027BC dual J-K flip-flops are monolithic complementary MOS CMOS integrated circuits constructed with N- and P-channel enhancement mode transistors. Each flip-flop has independent J, K, set, reset, and clock inputs and buffered Q and Q outputs. These flip-flops are edge sensitive to the clock input and change state on the positive-going transition of the clock pulses. Set or reset is independent of the clock and is accomplished by a high level on the respective input. All inputs are protected against damage due to static discharge by diode clamps to VDD and VSS. s Wide supply voltage range 3.0V to 15V s High noise immunity VDD typ. s Low power TTL compatibility Fan out of 2 driving 74L or 1 driving 74LS s Low power 50 nW typ. s Medium speed operation 12 MHz typ. with 10V supply Ordering Code: Order Number CD4027BCM CD4027BCN Package Number Package Description M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Connection Diagram Top View Truth Table Inputs tn−1 Note 1 Outputs tn Note 2 CL J K S R Q I X O X X O X I X O I O I X No Change XX I OX I XXO I X O XX I X I I = HIGH Level O = LOW Level X = Don’t Care = LOW-to-HIGH = HIGH-to-LOW Note 1 tn−1 refers to the time interval prior to the positive clock pulse transition Note 2 tn refers to the time intervals after the positive clock pulse transition Note 3 Level Change 2004 Fairchild Semiconductor Corporation DS005958 CD4027BC Logic Diagram CD4027BC Absolute Maximum Ratings Note 4 Note 5 DC Supply Voltage VDD VDC to +18 VDC Input Voltage VIN −0.5V to VDD VDC Storage Temperature Range TS −65°C to +150°C Power Dissipation PD Dual-In-Line 700 mW

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CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset

CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset

The CD4027BC dual J-K flip-flops are monolithic complementary MOS CMOS integrated circuits constructed with N- and P-channel enhancement mode transistors. Each flip-flop has independent J, K, set, reset, and clock inputs and buffered Q and Q outputs. These flip-flops are edge sensitive to the clock input and change state on the positive-going transition of the clock pulses. Set or reset is independent of the clock and is accomplished by a high level on the respective input.

All inputs are protected against damage due to static discharge by diode clamps to VDD and VSS.
s Wide supply voltage range 3.0V to 15V s High noise immunity VDD typ. s Low power TTL compatibility Fan out of 2 driving 74L
or 1 driving 74LS s Low power 50 nW typ. s Medium speed operation 12 MHz typ. with 10V
supply
Ordering Code:

Order Number CD4027BCM CD4027BCN

Package Number

Package Description

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide

Connection Diagram

Top View

Truth Table

Inputs tn−1 Note 1

Outputs tn Note 2

CL J K S R Q

I X O X

X O X I X

O I O I X

No Change

XX I OX I

XXO I X O

XX I X I

I = HIGH Level O = LOW Level X = Don’t Care
= LOW-to-HIGH = HIGH-to-LOW

Note 1 tn−1 refers to the time interval prior to the positive clock pulse transition

Note 2 tn refers to the time intervals after the positive clock pulse transition

Note 3 Level Change
2004 Fairchild Semiconductor Corporation DS005958

CD4027BC

Logic Diagram

CD4027BC

Absolute Maximum Ratings Note 4

Note 5

DC Supply Voltage VDD

VDC to +18 VDC

Input Voltage VIN
−0.5V to VDD VDC

Storage Temperature Range TS
−65°C to +150°C

Power Dissipation PD

Dual-In-Line
700 mW

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Datasheet ID: CD4027BCN 513563