74VHC4046MTC

74VHC4046MTC Datasheet

74VHC4046 CMOS Phase Lock Loop

Part	Datasheet
74VHC4046MTC	74VHC4046MTC (pdf)

Related Parts	Information
74VHC4046M	74VHC4046M
74VHC4046MTCX	74VHC4046MTCX
74VHC4046MX	74VHC4046MX
74VHC4046N	74VHC4046N

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74VHC4046 CMOS Phase Lock Loop 74VHC4046 CMOS Phase Lock Loop The VHC4046 is a low power phase lock loop utilizing advanced silicon-gate CMOS technology to obtain high frequency operation both in the phase comparator and VCO sections. This device contains a low power linear voltage controlled oscillator VCO , a source follower, and three phase comparators. The three phase comparators have a common signal input and a common comparator input. The signal input has a self biasing amplifier allowing signals to be either capacitively coupled to the phase comparators with a small signal or directly coupled with standard input logic levels. This device is similar to the CD4046 except that the Zener diode of the metal gate CMOS device has been replaced with a third phase comparator. Phase Comparator I is an exclusive OR XOR gate. It provides a digital error signal that maintains a 90 phase shift between the VCO’s center frequency and the input signal 50% duty cycle input waveforms . This phase detector is more susceptible to locking onto harmonics of the input frequency than phase comparator I, but provides better noise rejection. Phase comparator III is an SR flip-flop gate. It can be used to provide the phase comparator functions and is similar to the first comparator in performance. Phase comparator II is an edge sensitive digital sequential network. Two signal outputs are provided, a comparator output and a phase pulse output. The comparator output is a 3-STATE output that provides a signal that locks the VCO output signal to the input signal with 0 phase shift between them. This comparator is more susceptible to noise throw- ing the loop out of lock, but is less likely to lock onto harmonics than the other two comparators. In a typical application any one of the three comparators feed an external filter network which in turn feeds the VCO input. This input is a very high impedance CMOS input which also drives the source follower. The VCO’s operating frequency is set by three external components connected to the C1A, C1B, R1 and R2 pins. An inhibit pin is provided to disable the VCO and the source follower, providing a method of putting the IC in a low power state. The source follower is a MOS transistor whose gate is connected to the VCO input and whose drain connects the Demodulator output. This output normally is used by tying a resistor from pin 10 to ground, and provides a means of looking at the VCO input without loading down modifying the characteristics of the PLL filter. s Low dynamic power consumption VCC = 4.5V s Maximum VCO operating frequency 12 MHz VCC = 4.5V s Fast comparator response time VCC = 4.5V Comparator I 25 ns Comparator II 30 ns Comparator III 25 ns s VCO has high linearity and high temperature stability s Pin and function compatible with the 74HC4046 Ordering Code: Order Number Package Number Package Description 74VHC4046M M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 74VHC4046MTC MTC16 16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 74VHC4046N N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. 2003 Fairchild Semiconductor Corporation DS011675 74VHC4046 Connection Diagram Block Diagram 74VHC4046 Absolute Maximum Ratings Note 1 Note 2 Supply Voltage VCC DC Input Voltage VIN DC Output Voltage VOUT Clamp Diode Current IIK, IOK DC Output Current per pin IOUT DC VCC or GND Current, per pin ICC Storage Temperature Range TSTG Power Dissipation PD Note 3 S.O. Package only Lead Temperature TL Soldering 10 seconds to + 7.0V to VCC +1.5V to VCC + 0.5V ±20 mA ±25 mA ±50 mA −65°C +150°C 600 mW 500 mW 260°C Recommended Operating Conditions Min Max Units Supply Voltage VCC DC Input or Output Voltage VIN, VOUT Operating Temperature Range TA −40 +85 °C Input Rise or Fall Times tr, tf VCC = 2.0V 1000 ns VCC = 4.5V 500 ns VCC = 6.0V 400 ns Note 1 Maximum Ratings are those values beyond which damage to the device may occur. Note 2 Unless otherwise specified all voltages are referenced to ground. Note 3 Power Dissipation temperature derating plastic “N” package − 12 mW/°C from 65°C to 85°C. DC Electrical Characteristics Note 4 Parameter Conditions TA=25°C TA=−40 to 85°C Units Guaranteed Limits

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74VHC4046 CMOS Phase Lock Loop
74VHC4046 CMOS Phase Lock Loop

The VHC4046 is a low power phase lock loop utilizing advanced silicon-gate CMOS technology to obtain high frequency operation both in the phase comparator and VCO sections. This device contains a low power linear voltage controlled oscillator VCO , a source follower, and three phase comparators. The three phase comparators have a common signal input and a common comparator input. The signal input has a self biasing amplifier allowing signals to be either capacitively coupled to the phase comparators with a small signal or directly coupled with standard input logic levels. This device is similar to the CD4046 except that the Zener diode of the metal gate CMOS device has been replaced with a third phase comparator.

Phase Comparator I is an exclusive OR XOR gate. It provides a digital error signal that maintains a 90 phase shift between the VCO’s center frequency and the input signal 50% duty cycle input waveforms . This phase detector is more susceptible to locking onto harmonics of the input frequency than phase comparator I, but provides better noise rejection.

Phase comparator III is an SR flip-flop gate. It can be used to provide the phase comparator functions and is similar to the first comparator in performance.

Phase comparator II is an edge sensitive digital sequential network. Two signal outputs are provided, a comparator output and a phase pulse output. The comparator output is a 3-STATE output that provides a signal that locks the VCO output signal to the input signal with 0 phase shift between them. This comparator is more susceptible to noise throw-
ing the loop out of lock, but is less likely to lock onto harmonics than the other two comparators.

In a typical application any one of the three comparators feed an external filter network which in turn feeds the VCO input. This input is a very high impedance CMOS input which also drives the source follower. The VCO’s operating frequency is set by three external components connected to the C1A, C1B, R1 and R2 pins. An inhibit pin is provided to disable the VCO and the source follower, providing a method of putting the IC in a low power state.

The source follower is a MOS transistor whose gate is connected to the VCO input and whose drain connects the Demodulator output. This output normally is used by tying a resistor from pin 10 to ground, and provides a means of looking at the VCO input without loading down modifying the characteristics of the PLL filter.
s Low dynamic power consumption VCC = 4.5V s Maximum VCO operating frequency 12 MHz

VCC = 4.5V s Fast comparator response time VCC = 4.5V

Comparator I 25 ns

Comparator II 30 ns

Comparator III 25 ns s VCO has high linearity and high temperature stability s Pin and function compatible with the 74HC4046
Ordering Code:

Order Number Package Number

Package Description
74VHC4046M

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow
74VHC4046MTC

MTC16
16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
74VHC4046N

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
2003 Fairchild Semiconductor Corporation DS011675
74VHC4046

Connection Diagram Block Diagram
74VHC4046

Absolute Maximum Ratings Note 1

Note 2

Supply Voltage VCC DC Input Voltage VIN DC Output Voltage VOUT Clamp Diode Current IIK, IOK DC Output Current per pin IOUT DC VCC or GND Current,
per pin ICC Storage Temperature Range TSTG Power Dissipation PD

Note 3

S.O. Package only

Lead Temperature TL Soldering 10 seconds
to + 7.0V to VCC +1.5V to VCC + 0.5V
±20 mA ±25 mA
±50 mA −65°C +150°C
600 mW 500 mW
260°C

Recommended Operating Conditions

Min Max Units

Supply Voltage VCC

DC Input or Output Voltage

VIN, VOUT

Operating Temperature Range TA −40 +85 °C

Input Rise or Fall Times
tr, tf

VCC = 2.0V
1000 ns

VCC = 4.5V
500 ns

VCC = 6.0V
400 ns

Note 1 Maximum Ratings are those values beyond which damage to the
device may occur.

Note 2 Unless otherwise specified all voltages are referenced to ground.

Note 3 Power Dissipation temperature derating plastic “N” package − 12 mW/°C from 65°C to 85°C.

DC Electrical Characteristics Note 4

Parameter

Conditions

TA=25°C

TA=−40 to 85°C Units

Guaranteed Limits

More datasheets: 3541H-1-103 | 3541H-1-102 | 3540S-1-502 | 3540S-1-104 | 3540S-1-102 | 1465 | 3242 | 74VHC4046M | 74VHC4046MTCX | 74VHC4046MX

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Datasheet ID: 74VHC4046MTC 513489