74VCXF162835MTX

74VCXF162835MTX Datasheet

74VCXF162835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Outputs and Series Resistors in Outputs

Part	Datasheet
74VCXF162835MTX	74VCXF162835MTX (pdf)

Related Parts	Information
74VCXF162835MTD	74VCXF162835MTD

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74VCXF162835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Outputs and Series Resistors in Outputs 74VCXF162835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Outputs and Series Resistors in Outputs The VCXF162835 low voltage 18-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes. Data flow is controlled by output-enable OE , latch-enable LE , and clock CLK inputs. The device operates in Transparent Mode when LE is held HIGH. The device operates in clocked mode when LE is LOW and CLK is toggled. Data transfers from the Inputs In to Outputs On a Positive Edge Transition of the Clock. When OE is LOW, the output data is enabled. When OE is HIGH the output port is in a high impedance state. The VCXF162835 is designed with series resistors in the outputs. This design reduces noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters. The 74VCXF162835 is designed for low voltage 1.65V to 3.6V VCC applications with I/O capability up to 3.6V. The 74VCXF162835 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. s Compatible with PC133 DIMM module specifications s VCC specifications provided s 3.6V tolerant outputs s series resistors in outputs s tPD CLK to On ns max for 3.0V to 3.6V VCC ns max for 2.3V to 2.7V VCC ns max for 1.65V to 1.95V VCC s Power-down high impedance outputs s Static Drive IOH/IOL ±12 mA 3.0V VCC ±8 mA 2.3V VCC ±3 mA 1.65V VCC s Latchup performance exceeds 300 mA s ESD performance: Human body model > 2000V Machine model >200V Ordering Code: Order Number Package Number Package Description 74VCXF162835MTD MTD56 56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide [TUBES] 74VCXF162835MTX MTD56 56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Note 1 [TAPE and REEL] Note 1 Use this Order Number to receive devices in Tape and Reel. 2000 Fairchild Semiconductor Corporation DS500259 74VCXF162835 Connection Diagram Logic Diagram Pin Descriptions Pin Names OE LE CLK I1 - I18 O1 - O18 Output Enable Input Active LOW Latch Enable Input Clock Input Data Inputs 3-STATE Outputs Truth Table Inputs Outputs H = Logic HIGH L = Logic LOW X = Don’t Care, but not floating Z = High Impedance = LOW-to-HIGH Clock Transition O0 Note 2 O0 Note 3 Note 2 Output level before the indicated steady-state input conditions were established provided that CLK was HIGH before LE went LOW. Note 3 Output level before the indicated steady-state input conditions were established. 74VCXF162835 Absolute Maximum Ratings Note 4 Supply Voltage VCC DC Input Voltage VI Output Voltage VO Outputs 3-STATE −0.5V to +4.6V −0.5V to VCC + 0.5V −0.5V to +4.6V Outputs Active Note 5 DC Input Diode Current IIK VI < −0.5V VI > VCC + 0.5V Note 6 DC Output Diode Current IOK VO < 0V VO > VCC DC Output Source/Sink Current −0.5V to VCC + 0.5V −50 mA +50 mA −50 mA +50 mA IOH/IOL DC VCC or Ground Current per Supply Pin ICC or Ground Storage Temperature Range TSTG ±50 mA ±100 mA −65°C to +150°C

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74VCXF162835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Outputs and Series Resistors in Outputs
74VCXF162835

Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Outputs and Series Resistors in Outputs

The VCXF162835 low voltage 18-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes.

Data flow is controlled by output-enable OE , latch-enable LE , and clock CLK inputs. The device operates in Transparent Mode when LE is held HIGH. The device operates in clocked mode when LE is LOW and CLK is toggled. Data transfers from the Inputs In to Outputs On a Positive Edge Transition of the Clock. When OE is LOW, the output data is enabled. When OE is HIGH the output port is in a high impedance state.

The VCXF162835 is designed with series resistors in the outputs. This design reduces noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters.

The 74VCXF162835 is designed for low voltage 1.65V to 3.6V VCC applications with I/O capability up to 3.6V.

The 74VCXF162835 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
s Compatible with PC133 DIMM module specifications s VCC specifications provided s 3.6V tolerant outputs s series resistors in outputs s tPD CLK to On
ns max for 3.0V to 3.6V VCC ns max for 2.3V to 2.7V VCC ns max for 1.65V to 1.95V VCC s Power-down high impedance outputs s Static Drive IOH/IOL ±12 mA 3.0V VCC ±8 mA 2.3V VCC ±3 mA 1.65V VCC s Latchup performance exceeds 300 mA s ESD performance:

Human body model > 2000V Machine model >200V
Ordering Code:

Order Number

Package Number

Package Description
74VCXF162835MTD MTD56 56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide [TUBES]
74VCXF162835MTX MTD56 56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide

Note 1
[TAPE and REEL]

Note 1 Use this Order Number to receive devices in Tape and Reel.
2000 Fairchild Semiconductor Corporation DS500259
74VCXF162835

Connection Diagram Logic Diagram

Pin Descriptions

Pin Names

OE LE CLK I1 - I18 O1 - O18

Output Enable Input Active LOW Latch Enable Input Clock Input Data Inputs 3-STATE Outputs

Truth Table

Inputs

Outputs

H = Logic HIGH L = Logic LOW X = Don’t Care, but not floating Z = High Impedance = LOW-to-HIGH Clock Transition

O0 Note 2

O0 Note 3

Note 2 Output level before the indicated steady-state input conditions were established provided that CLK was HIGH before LE went LOW.

Note 3 Output level before the indicated steady-state input conditions were established.
74VCXF162835

Absolute Maximum Ratings Note 4

Supply Voltage VCC DC Input Voltage VI Output Voltage VO

Outputs 3-STATE
−0.5V to +4.6V −0.5V to VCC + 0.5V
−0.5V to +4.6V

Outputs Active Note 5

DC Input Diode Current IIK VI < −0.5V VI > VCC + 0.5V Note 6

DC Output Diode Current IOK VO < 0V VO > VCC

DC Output Source/Sink Current
−0.5V to VCC + 0.5V
−50 mA +50 mA
−50 mA +50 mA

IOH/IOL DC VCC or Ground Current per

Supply Pin ICC or Ground Storage Temperature Range TSTG
±50 mA
±100 mA −65°C to +150°C

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Datasheet ID: 74VCXF162835MTX 513479