74VCX32500G

74VCX32500G Datasheet


74VCX32500 Low Voltage 36-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs

Part Datasheet
74VCX32500G 74VCX32500G 74VCX32500G (pdf)
Related Parts Information
74VCX32500GX 74VCX32500GX 74VCX32500GX
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74VCX32500 Low Voltage 36-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs
74VCX32500 Low Voltage 36-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs

The VCX32500 is an 36-bit universal bus transceiver which combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.

Data flow in each direction is controlled by output-enable OEAB and OEBA , latch-enable LEAB and LEBA , and clock CLKAB and CLKBA inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the HIGH-to-LOW transition of CLKAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in a highimpedance state.

Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are complementary OEAB is active HIGH and OEBA is active LOW .

The VCX32500 is designed for low voltage 1.4V to 3.6V VCC applications with I/O capability up to 3.6V.

The 74VCX32500 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
s 1.4V to 3.6V VCC supply operation s 3.6V tolerant inputs and outputs s tPD A to B, B to A
ns max for 3.0V to 3.6V VCC s Power-down high impedance inputs and outputs s Supports live insertion/withdrawal Note 1 s Static Drive IOH/IOL
±24 mA 3.0V VCC s Uses patented noise/EMI reduction circuitry s Latchup performance exceeds 300 mA s ESD performance:

Human body model > 2000V Machine model >200V s Packaged in plastic Fine-Pitch Ball Grid Array FBGA

Note 1 To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a pull-up resistor and OEAB should be tied to GND through a pull-down resistors the minimum value of the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:

Order Number Package Number

Package Description
74VCX32500G Note 2 Note 3

BGA114A 114-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide
Note 2 Ordering Code “G” indicates Trays.
Note 3 Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
2003 Fairchild Semiconductor Corporation DS500403
74VCX32500

Connection Diagram

Top Thru View

Pin Descriptions

Pin Names

OEABn

Output Enable Input for A to B Direction Active HIGH

OEBAn

Output Enable Input for B to A Direction Active LOW

LEABn, LEBAn Latch Enable Inputs

CLKABn, CLKBAn

Clock Inputs

Side A Inputs or 3-STATE Outputs

Side B Inputs or 3-STATE Outputs

FBGA Pin Assignments

A 1A2 1A1 LEAB1 CLKAB1 1B1

B 1A4 1A3 OEAB1 GND

C 1A6 1A5 GND

D 1A8 1A7 VCC

E 1A10 1A9 GND

F 1A12 1A11 GND
1B11

G 1A14 1A13 VCC
1B13

H 1A15 1A16 GND
1B16
1B2 1B4 1B6 1B8 1B10 1B12 1B14 1B15

J 1A17 1A18 OEBA1 CLKBA1 1B18 1B17

K NC LEAB2 LEBA1 GND CLKAB2 NC

L 2A2 2A1 OEAB2 GND

M 2A4 2A3 GND

N 2A6 2A5 VCC

P 2A8 2A7 GND

R 2A10 2A9 GND
2B10

T 2A12 2A11 VCC
2B11 2B12

U 2A14 2A13 GND
2B13 2B14
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Datasheet ID: 74VCX32500G 513477