74VCX16839MTDX

74VCX16839MTDX Datasheet

74VCX16839 Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs

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74VCX16839MTDX	74VCX16839MTDX (pdf)

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74VCX16839MTD	74VCX16839MTD

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74VCX16839 Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs 74VCX16839 Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs The VCX16839 contains twenty non-inverting selectable buffered or registered paths. The device can be configured to operate in a registered, or flow through buffer mode by utilizing the register enable REGE and Clock CLK signals. The device operates in a 20-bit word wide mode. All outputs can be placed into 3-STATE through use of the OE pin. These devices are ideally suited for buffered or registered 168 pin and 200 pin SDRAM DIMM memory modules. The 74VCX16839 is designed for low voltage 1.65V to 3.6V VCC applications with I/O compatibility up to 3.6V. The 74VCX16839 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. s Compatible with PC100 and PC133 DIMM module specifications s VCC supply operation s 3.6V tolerant inputs and outputs s tPD CLK to On ns max for 3.0V to 3.6V VCC ns max for 2.3V to 2.7V VCC ns max for 1.65V to 1.95V VCC s Power-off high impedance inputs and outputs s Supports live insertion and withdrawal Note 1 s Static Drive IOH/IOL ±24 mA 3.0V VCC ±18 mA 2.3V VCC ±6 mA 1.65V VCC s Uses patented noise/EMI reduction circuitry s Latch-up performance exceeds 300 mA s ESD performance Human body model > 2000V Machine model > 200V Note 1 To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor the minimum value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number Package Descriptions 74VCX16839MTD MTD56 56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names OE CLK REGE Description Output Enable Input Active LOW Inputs Outputs Clock Input Register Enable Input 2000 Fairchild Semiconductor Corporation DS500105 74VCX16839 Connection Diagram Logic Diagram Truth Table Inputs Outputs REGE H = Logic HIGH L = Logic LOW X = Don’t Care, but not floating Z = High Impedance = LOW-to-HIGH Clock Transition Functional Description The 74VCX16839 consists of twenty selectable non-inverting buffers or registers with word wide modes. Mode functionality is selected through operation of the CLK and REGE pin as shown by the truth table. When REGE is held at a logic HIGH the device operates as a 20-bit register. Data is transferred from In to On the rising edge of the CLK input. When the REGE pin is held at a logic LOW the device operates in a flow through mode and data propagates directly from the In to the On outputs. All outputs can be 3-stated by holding the OE pin at a logic HIGH. 74VCX16839 Absolute Maximum Ratings Note 2 Supply Voltage VCC DC Input Voltage VI Output Voltage VO Outputs 3-STATE Outputs Active Note 3 DC Input Diode Current IIK VI < 0V DC Output Diode Current IOK VO < 0V VO > VCC DC Output Source/Sink Current IOH/IOL DC VCC or GND Current per Supply Pin ICC or GND Storage Temperature Range TSTG −0.5V to +4.6V −0.5V to +4.6V −0.5V to +4.6V −0.5V to VCC +0.5V −50 mA −50 mA +50 mA ±50 mA ±100 mA −65°C to +150°C Recommended Operating Conditions Note 4 Power Supply Operating 1.65V to 3.6V Data Retention Only 1.2V to 3.6V Input Voltage −0.3V to +3.6V Output Voltage VO Output in Active States Output in “OFF” State 0V to VCC 0V to 3.6V

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74VCX16839 Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs
74VCX16839 Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs

The VCX16839 contains twenty non-inverting selectable buffered or registered paths. The device can be configured to operate in a registered, or flow through buffer mode by utilizing the register enable REGE and Clock CLK signals. The device operates in a 20-bit word wide mode. All outputs can be placed into 3-STATE through use of the OE pin. These devices are ideally suited for buffered or registered 168 pin and 200 pin SDRAM DIMM memory modules.

The 74VCX16839 is designed for low voltage 1.65V to 3.6V VCC applications with I/O compatibility up to 3.6V.

The 74VCX16839 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
s Compatible with PC100 and PC133 DIMM module specifications
s VCC supply operation s 3.6V tolerant inputs and outputs s tPD CLK to On
ns max for 3.0V to 3.6V VCC ns max for 2.3V to 2.7V VCC ns max for 1.65V to 1.95V VCC s Power-off high impedance inputs and outputs s Supports live insertion and withdrawal Note 1 s Static Drive IOH/IOL ±24 mA 3.0V VCC ±18 mA 2.3V VCC ±6 mA 1.65V VCC s Uses patented noise/EMI reduction circuitry s Latch-up performance exceeds 300 mA s ESD performance Human body model > 2000V Machine model > 200V

Note 1 To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor the minimum value of the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:

Order Number Package Number

Package Descriptions
74VCX16839MTD

MTD56
56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Pin Descriptions

Pin Names

OE CLK REGE

Description Output Enable Input Active LOW Inputs Outputs Clock Input Register Enable Input
2000 Fairchild Semiconductor Corporation DS500105
74VCX16839

Connection Diagram Logic Diagram

Truth Table

Inputs

Outputs

REGE

H = Logic HIGH L = Logic LOW X = Don’t Care, but not floating Z = High Impedance = LOW-to-HIGH Clock Transition

Functional Description

The 74VCX16839 consists of twenty selectable non-inverting buffers or registers with word wide modes. Mode functionality is selected through operation of the CLK and REGE pin as shown by the truth table. When REGE is held at a logic HIGH the device operates as a 20-bit register. Data is transferred from In to On the rising edge of the CLK input. When the REGE pin is held at a logic LOW the device operates in a flow through mode and data propagates directly from the In to the On outputs. All outputs can be 3-stated by holding the OE pin at a logic HIGH.
74VCX16839

Absolute Maximum Ratings Note 2

Supply Voltage VCC DC Input Voltage VI Output Voltage VO

Outputs 3-STATE

Outputs Active Note 3

DC Input Diode Current IIK VI < 0V DC Output Diode Current IOK

VO < 0V VO > VCC DC Output Source/Sink Current

IOH/IOL DC VCC or GND Current per

Supply Pin ICC or GND Storage Temperature Range TSTG
−0.5V to +4.6V −0.5V to +4.6V
−0.5V to +4.6V −0.5V to VCC +0.5V
−50 mA
−50 mA +50 mA
±50 mA
±100 mA −65°C to +150°C

Recommended Operating Conditions Note 4

Power Supply

Operating
1.65V to 3.6V

Data Retention Only
1.2V to 3.6V

Input Voltage
−0.3V to +3.6V

Output Voltage VO Output in Active States Output in “OFF” State
0V to VCC 0V to 3.6V

More datasheets: H-300C-1-180 | H-300C-2-100 | H-300C-2-120 | H-300C-1-100 | H-300C-2-180 | H-300C-2-140 | H-300C-2-160 | 2414 | FQP6N25 | TSL257T

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Datasheet ID: 74VCX16839MTDX 513470